參數(shù)資料
型號(hào): LTC1282BCN#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 2/24頁(yè)
文件大小: 0K
描述: IC A/D CONV SAMPLING W/REF 24DIP
標(biāo)準(zhǔn)包裝: 15
位數(shù): 12
采樣率(每秒): 140k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 24mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
10
LTC1282
FU TIO AL BLOCK DIAGRA
UU
W
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
CONVERSION DETAILS
The LTC1282 uses a successive approximation and an
internal sample-and-hold circuitry to convert an analog
signal to a 12-bit parallel or 2-byte output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. Please refer to the Digital Interface section
for the data format.
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the sample phase, and the comparator
offset is nulled by the feedback switch. In this sample
phase, a minimum delay of 1.14
s will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge to the summing
junction. This input charge is successively compared with
the binary-weighted charges supplied by the capacitive
DAC. Bit decisions are made by the high speed comparator.
At the end of a conversion, the DAC output balances the AIN
input charge. The SAR contents (a 12-bit data word) which
represent the AIN are loaded into the 12-bit latch.
VDAC
LTC1282 F01
+
CDAC
DAC
SAMPLE
HOLD
CSAMPLE
S
A
R
12-BIT
LATCH
COMPARATOR
SAMPLE
SI
AIN
Figure 1. AIN Input
CSAMPLE
CONTROL
LOGIC
INTERNAL
CLOCK
SUCCESSIVE
APPROXIMATION
REGISTER
12
OUTPUT
LATCHES
D11
D0/8
BUSY
1.2V
REFERENCE
VREF(OUT)
DGND
AGND
AIN
SAMPLE
HOLD
SAMPLE
VSS (–3V FOR BIPOLAR MODE,
AGND FOR UNIPOLAR MODE)
VDD
HBEN
CS
RD
LTC1282 FBD
12-BIT
CAPACITIVE
DAC
COMPARATOR
+
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