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參數(shù)資料
| 型號(hào)： | LTC1266IS#TR-3.3 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SO-16 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 245K |
| 代理商： | LTC1266IS#TR-3.3 |
15
LTC1266
LTC1266-3.3/LTC1266-5
operation, the DC supply current represents the lone (and
unavoidable) loss component which continues to become
a higher percentage as output current is reduced. As
expected the I2R losses dominate at high load currents.
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, gener-
ally account for less than 2% total additional loss.
Design Example
As a design example, assume VIN = 5V (nominal),
VOUT = 3.3V, IMAX = 5A and f = 200kHz; RSENSE, CT and L
can immediately be calculated:
RSENSE = 100mV/5 = 0.02
tOFF = (1/200kHz) [1 – (3.3/5)] = 1.7s
CT = 1.7s/(1.3 104) = 130pF
LMIN = 5.1 105 0.02 130pF 3.3V = 5H
Assume that the MOSFET dissipations are to be limited to
PT = PB = 2W.
If TA = 40°C and the thermal resistance of each MOSFET
is 50
°C/W, then the junction temperatures will be 140°C
and
δT = δB = 0.60. The required RDS(ON) for each MOSFET
can now be calculated:
TS RDS(ON) =
5(2)
3.3(5)2 (1.60)
= 0.076
BS RDS(ON) =
5(2)
1.7(5)2 (1.60)
= 0.147
The topside FET requirement can be met by an N-channel
Si9410DY which has an RDS(ON) of about 0.04 at
VGS = 5V. The bottom-side FET requirement is exceeded
by an Si9410DY. Note that the most stringent requirement
for the bottom-side MOSFET is with VOUT = 0 (i.e., short
circuit). During a continuous short circuit, the worst-case
dissipation rises to:
PB = ISC(AVG)2 RDS(ON) (1 + δB)
With the 0.02
sense resistor, ISC(AVG) ≈ 6A will result,
increasing the 0.04
bottom-sideFETdissipationto2.3W.
CIN will require an RMS current rating of at least 2.5A at
temperature and COUT will require an ESR of 0.02 for
optimum efficiency.
Now allow VIN to drop to its minimum value. The minimum
VIN can be calculated from the maximum duty cycle and
voltage drop across the topside FET,
VMIN =
DMAX
VOUT + ILOAD (RDS(ON) + RL + RSENSE)
= 4.0V
At this lower input voltage, the operating frequency de-
creases and the topside FET will be conducting most of the
time, causing the power dissipation to increase.
At dropout,
fMIN =
1
tON (MAX) + tOFF
= 16kHz
PT = I2LOAD RDS(ON) (1 + δT) DMAX
This last step is necessary to assure that the power
dissipation and junction temperature of the topside FET
are not exceeded.
These last calculations assume that Power VIN is high
enough to keep the topside FET fully turned on at dropout,
as would be the case with the Figure 11circuit. If this isn’t
true (as with the Figure 1 circuit) the RDS(ON) will increase
which in turn increases VMIN and PT.
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1266 adjustable version is used with an external
resistive divider from VOUT to VFB, Pin 10. The regulated
voltage is determined by:
VOUT = 1.265
)
)1+ R2
R1
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1266.
For Figure 1 applications with VOUT below 2V, or when
RSENSE is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.
APPLICATIO S I FOR ATIO
WU
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