參數(shù)資料
型號(hào)： LTC1261CS84.5
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHED CAPACITOR REGULATOR, 550 kHz SWITCHING FREQ-MAX, PDSO8
封裝： PLASTIC, SOIC-8
文件頁(yè)數(shù)： 15/16頁(yè)
文件大?。?/td> 266K
代理商： LTC1261CS84.5
8
LTC1261
APPLICATIONS INFORMATION
WU
U
OUTPUT RIPPLE
Output ripple in the LTC1261 comes from two sources;
voltage droop at the output capacitor between clocks and
frequency response of the regulation loop. Voltage droop
is easy to calculate. With a typical clock frequency of
550kHz, the charge on the output capacitor is refreshed
once every 1.8
s. With a 15mA load and a 3.3F output
capacitor, the output will droop by:
ILOAD ×
= 15mA
×
t
COUT
)
= 8.2mV
1.8
s
3.3
F
)
This can be a significant ripple component when the
output is heavily loaded, especially if the output capacitor
is small. If absolute minimum output ripple is required, a
10
F or greater output capacitor should be used.
Regulation loop frequency response is the other major
contributor to output ripple. The LTC1261 regulates the
output voltage by limiting the amount of charge trans-
ferred to the output capacitor on a cycle-by-cycle basis.
The output voltage is sensed at the ADJ pin (COMP for
fixed output versions) through an internal or external
resistor divider from the OUT pin to ground. As the flying
capacitors are first connected to the output, the output
voltage begins to change quite rapidly. As soon as it
exceeds the set point COMP1 trips, switching the state of
the charge pump and stopping the charge transfer. Be-
cause the RC time constant of the capacitors and the
switches is quite short, the ADJ pin must have a wide AC
bandwidth to be able to respond to the output in time.
External parasitic capacitance at the ADJ pin can reduce
the bandwidth to the point where the comparator cannot
respond by the time the clock pulse finishes. When this
happens the comparator will allow a few complete pulses
through, then overcorrect and disable the charge pump
until the output drops below the set point. Under these
conditions the output will remain in regulation but the
output ripple will increase as the comparator “hunts” for
the correct value.
To prevent this from happening, an external capacitor can
be connected from ADJ (or COMP for fixed output parts)
to ground to compensate for external parasitics and in-
crease the regulation loop bandwidth (Figure 3). This
sounds counterintuitive until we remember that the inter-
nal reference is generated with respect to OUT, not ground.
COMP 1
1.24V
R2
VOUT
ADJ/COMP
RESISTORS ARE
INTERNAL FOR
FIXED OUTPUT PARTS
LTC1261 F03
R1
CC
100pF
TO CHARGE
PUMP
REF
+
–
Figure 3. Regulator Loop Compensation
The feedback loop actually sees ground as its “output,”
thus the compensation capacitor should be connected
across the “top” of the resistor divider, from ADJ (or
COMP) to ground. By the same token, avoid adding
capacitance between ADJ (or COMP) and VOUT. This will
slow down the feedback loop and increase output ripple.
A 100pF capacitor from ADJ or COMP to ground will
compensate the loop properly under most conditions.
OUTPUT FILTERING
If extremely low output ripple (< 5mV) is required, addi-
tional output filtering is required. Because the LTC1261
uses a high 550kHz switching frequency, fairly low value
RC or LC networks can be used at the output to effectively
filter the output ripple. A 10
series output resistor and a
3.3
F capacitor will cut output ripple to below 3mV (Figure
4). Further reductions can be obtained with larger filter
capacitors or by using an LC output filter.
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