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參數(shù)資料
| 型號： | LTC1164-7CSW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER LP 8TH ORDER 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 濾波器類型： | 線性相位，低通開關(guān)電容器 |
| 頻率 - 截止或中心： | 100kHz |
| 濾波器數(shù)： | 1 |
| 濾波器階數(shù)： | 8th |
| 電源電壓： | 4.75 V ~ 16 V，±2.375 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
12
LTC1164-7
11647fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 5
100
s/DIV
2V/DIV
INPUT = 1kHz
± 3V
fCLK = 500kHz
fC = 10kHz
VS = ±7.5V
1164-7 F05
INPUT
90%
50%
10%
OUTPUT
tr
td
ts
1164-7 F06
RISE TIME (tr) =
±5%
0.39
fCUTOFF
SETTLING TIME (ts) =
±5%
(TO 1% of OUTPUT)
2.2
fCUTOFF
TIME DELAY (td) = GROUP DELAY ≈
(TO 50% OF OUTPUT)
1.2
fCUTOFF
Figure 6
Aliasing
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1164-7 case
at 100:1, an input signal whose frequency is in the range
of fCLK ±3%, will be aliased back into the filter’s passband.
Transient Response
If, for instance, an LTC1164-7 operating with a 100kHz
clock and 1kHz cutoff frequency receives a 98kHz 10mV
input signal, a 2kHz, 143
VRMS alias signal will appear at
its output. When the LTC1164-7 operates with a clock-to-
cutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 11 shows details.
Table 11. Aliasing (fCLK = 100kHz)
INPUT FREQUENCY
OUTPUT LEVEL
OUTPUT FREQUENCY
(VIN = 1VRMS,
(Relative to Input,
(Aliased Frequency
fIN = fCLK ± fOUT)
0dB = 1VRMS)fOUT = ABS [fCLK ± fIN])
(kHz)
(dB)
(kHz)
50:1, fCUTOFF = 2kHz
190 (or 210)
–76.1
10.0
195 (or 205)
– 51.9
5.0
196 (or 204)
– 36.3
4.0
197(or 203)
– 18.4
3.0
198 (or 202)
– 3.0
2.0
199.5 (or 200.5)
– 0.2
0.5
100:1, fCUTOFF = 1kHz
97 (or 103)
–74.2
3.0
97.5 (or 102.5)
– 53.2
2.5
98 (or 102)
– 36.9
2.0
98.5 (or 101.5)
– 19.6
1.5
99 (or 101)
– 5.2
1.0
99.5 (or 100.5)
– 0.7
0.5
1V/DIV
5
s/DIV
1164-7 F07
Figure 7. Eye Diagram
VS = ±7.5V
fCLK = 1MHz
fC = 20kHz
(fCLK/fC) = 50:1
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