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參數(shù)資料
| 型號： | LTC1164-6CSW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER LP 8TH ORDER 16SOIC |
| 標準包裝： | 1,000 |
| 濾波器類型： | 橢圓或貝塞爾低通 |
| 頻率 - 截止或中心： | 30kHz |
| 濾波器數(shù)： | 1 |
| 濾波器階數(shù)： | 8th |
| 電源電壓： | 4.75 V ~ 16 V，±2.375 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
6
LTC1164-6
11646fa
CC
HARA TERISTICS
UW
A
TYPICALPERFOR
CE
THD + Noise vs RMS Input for
Single 5V (Elliptic Response)
INPUT (VRMS)
THD
+
NOISE
(dB)
1164-6 G18
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
0.1
1
2
A
B
A. GND = 2.5V
B. GND = 2V
(fCLK/fC) = 100:1 OR 50:1
fIN = 1kHz, TA = 25°C
THD + Noise vs RMS Input
(Elliptic Response)
INPUT (VRMS)
0.1
THD
+
NOISE
(dB)
15
1164-6 G17
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
VS = ±7.5V
VS = ±5V
(fCLK/fC) = 100:1 OR 50:1
fIN = 1kHz, TA = 25°C
Power Supply Current vs Power
Supply Voltage
POWER SUPPLY (V+ OR V–)
0
CURRENT
(mA)
12
11
10
9
8
7
6
5
4
3
2
1
0
13
6
8
1164-6 G19
10
24
5
7
9
–55
°C
25
°C
125
°C
2V/DIV
1ms/DIV
1164-6 G21
VS = ±7.5V, VIN = ±3V 100Hz SQUARE WAVE
fCLK = 800kHz, (fCLK/fC) = 160:1, fCUTOFF = 5kHz
LINEAR PHASE RESPONSE
Transient Response
1164-6 G20
1ms/DIV
VS = ±7.5V, VIN = ±3V 100Hz SQUARE WAVE
fCLK = 500kHz, (fCLK/fC) = 100:1, fCUTOFF = 5kHz
ELLIPTIC RESPONSE
2V/DIV
at least a 1
F capacitor (Figure 2). For single 5V operation
at the highest fCLK of 1MHz, Pins 3 and 5 should be biased
at 2V. This minimizes passband gain and phase variations
(see Typical Performance Characteristics curves: Maxi-
mum Passband for Single 5V, 50:1; and THD + Noise vs
RMS Input for Single 5V, 50:1).
V+ (Pins 4, 12):The V+ (Pin 4) and the V – (Pin 12) should
be bypassed with a 0.1
F capacitor to an adequate analog
ground. The filter’s power supplies should be isolated
from other digital or high voltage analog supplies. A low
noise linear supply is recommended. Using a switching
power supply will lower the signal-to-noise ratio of the
filter. The supply during power-up should have a slew rate
less than 1V/
s. When V+ is applied before V– and V–
(14-Lead Dual-In-Line Package)
PI FU CTIO S
U
UU
NC (Pins 1, 8, 13): Pins 1, 8, and 13 are not connected to
any internal circuit point on the device and should prefer-
ably be tied to analog ground.
VIN (Pin 2): The input pin is connected internally through
a 50k resistor tied to the inverting input of an op amp.
GND (Pins 3, 5): The filter performance depends on the
quality of the analog signal ground. For either dual or
single supply operation, an analog ground plane sur-
rounding the package is recommended. The analog ground
plane should be connected to any digital ground at a single
point. For dual supply operation, Pins 3 and 5 should be
connected to the analog ground plane. For single supply
operation Pins 3 and 5 should be biased at 1/2 supply and
they should be bypassed to the analog ground plane with
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