(VREF
參數(shù)資料
型號： LTC1090CSW#TR
廠商： Linear Technology
文件頁數(shù)： 4/28頁
文件大?。?/td> 0K
描述： IC DATA ACQ SYSTEM 10BIT 20SOIC
標準包裝： 1,000
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 10 b
采樣率（每秒）： 30k
數(shù)據(jù)接口： 串行
電壓電源： 單/雙電源
電源電壓： ±5V，5V，10V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 20-SOIC
包裝： 帶卷 (TR)
12
LTC1090
1090fc
Unipolar Output Code (UNI = 1)
INPUT VOLTAGE
OUTPUT CODE
INPUT VOLTAGE
(VREF = 5V)
1111111111
VREF – 1LSB
4.9951V
1111111110
VREF – 2LSB
4.9902V
0000000001
1LSB
0.0049V
0000000000
0V
Bipolar Output Code (UNI = 0)
INPUT VOLTAGE
OUTPUT CODE
INPUT VOLTAGE
(VREF = 5V)
0111111111
VREF – 1LSB
4.9902V
0111111110
VREF – 2LSB
4.9805V
0000000001
1LSB
0.0098V
0000000000
0V
1111111111
–1LSB
–0.0098V
1111111110
–2LSB
–0.0195V
1000000001
– (VREF) + 1LSB
–4.9902V
1000000000
– (VREF)–5.000V
MSB First/LSB First Format (MSBF)
The output data of the LTC1090 is programmed for MSB
first or LSB first sequence using the MSBF bit. For MSB
first output data the input word clocked to the LTC1090
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB first output data, the input
word clocked to the LTC1090 should always contain a zero
in the MSBF bit location. The MSBF bit in a given DIN word
will control the order of the next DOUT word. The MSBF bit
affects only the order of the output data word. The order
of the input word is unaffected by this bit.
MSBF
OUTPUT FORMAT
0LSB First
1
MSB First
Word Length (WL1, WL0)
The last two bits of the input word (WL1 and WL0) program
the output data word length of the LTC1090. Word lengths
of 8, 10, 12 or 16 bits can be selected according to the
following table. The WL1 and WL0 bits in a given DIN word
control the length of the present, not the next, DOUT word.
WL1 and WL0 are never “don’t cares” and must be set for
the correct DOUT word length even when a “dummy” DIN
word is sent. On any transfer cycle, the word length should
be made equal to the number of SCLK cycles sent by the
MPU.
WL1
WL0
OUTPUT WORD LENGTH
00
8 Bits
01
10 Bits
10
12 Bits
11
16 Bits
Figure 2 shows how the data output (DOUT) timing can be
controlled with word length selection and MSB/LSB first
format selection.
3. Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1090 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than 1
ACLK cycle. After a change of state on the CS input, the
LTC1090 waits for two falling edges of the ACLK before
recognizing a valid chip select. One indication of CS low
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
APPLICATIO S I FOR ATIO
WU
UU
HIGH Z
ACLK
VALID OUTPUT
DOUT
CS
LOW CS RECOGNIZED
INTERNALLY
HIGH CS RECOGNIZED
INTERNALLY
LTC1090 AI07
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