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參數資料
| 型號： | LTC1050HS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP CHOP-STBL W/CAPS 8SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數： | 1 |
| 轉換速率： | 4 V/µs |
| 增益帶寬積： | 2.5MHz |
| 電流 - 輸入偏壓： | 10pA |
| 電壓 - 輸入偏移： | 0.5µV |
| 電流 - 電源： | 1mA |
| 電壓 - 電源，單路/雙路(±)： | 4.75 V ~ 16 V，±2.38 V ~ 8 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
7
LTC1050
1050fb
Figure 2 is an example of the introduction of an unneces-
sary resistor to promote differential thermal balance.
Maintaining compensating junctions in close physical prox-
imity will keep them at the same temperature and reduce
thermal EMF errors.
U
S
A
O
PPLICATI
WU
U
IFOR ATIO
PACKAGE-INDUCED OFFSET VOLTAGE
Package-induced thermal EMF effects are another impor-
tant source of errors. It arises at the copper/kovar junctions
formed when wire or printed circuit traces contact a
package lead. Like all the previously mentioned thermal
EMF effects, it is outside the LTC1050’s offset nulling loop
and cannot be cancelled. The input offset voltage specifi-
cation of the LTC1050 is actually set by the package-induced
warm-up drift rather than by the circuit itself. The thermal
time constant ranges from 0.5 to 3 minutes, depending
upon package type.
OPTIONAL EXTERNAL CLOCK
An external clock is not required for the LTC1050 to
operate. The internal clock circuit of the LTC1050 sets the
nominal sampling frequency at around 2.5kHz. This fre-
quency is chosen such that it is high enough to remove the
amplifier 1/f noise, yet still low enough to allow internal
circuits to settle.The oscillator of the internal clock circuit
has a frequency 4 times the sampling frequency and its
output is brought out to Pin 5 through a 2k resistor. When
the LTC1050 operates without using an external clock,
Pin 5 should be left floating and capacitive loading on this
pin should be avoided. If the oscillator signal on Pin 5 is
used to drive other external circuits, a buffer with low
input capacitance is required to minimize loading on this
pin. Figure 3 illustrates the internal sampling frequency
versus capacitive loading at Pin 5.
–
+
LTC1050
OUTPUT
1050 F02
NOMINALLY
UNNECESSARY
RESISTOR USED TO
THERMALLY BALANCE
OTHER INPUT RESISTOR
RESISTOR LEAD, SOLDER
COPPER TRACE JUNCTION
LEAD WIRE/SOLDER/COPPER
TRACE JUNCTION
Figure 2
When connectors, switches, relays and/or sockets are
necessary they should be selected for low thermal EMF
activity. The same techniques of thermally balancing and
coupling the matching junctions are effective in reducing
the thermal EMF errors of these components.
Resistors are another source of thermal EMF errors.
Table 1 shows the thermal EMF generated for different
resistors. The temperature gradient across the resistor is
important, not the ambient temperature. There are two
junctions formed at each end of the resistor and if these
junctions are at the same temperature, their thermal
EMFs will cancel each other. The thermal EMF numbers
are approximate and vary with resistor value. High values
give higher thermal EMF.
Table 1. Resistor Thermal EMF
RESISTOR TYPE
THERMAL EMF/°C GRADIENT
Tin Oxide
~mV/°C
Carbon Composition
~450V/°C
Metal Film
~20V/°C
Wire Wound
Evenohm
~2V/°C
Manganin
~2V/°C
CAPACITANCE LOADING (pF)
1
SAMPLING
FREQUENCY,
f
S
(kHz)
2
10
5
100
1050 F03
3
VS = ± 5V
Figure 3. Sampling Frequency vs Capacitance Loading at Pin 5
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