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參數(shù)資料
| 型號： | LTC1043MD883C |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDIP18 |
| 封裝： | SIDE BRAZED, HERMETIC SEALED, DIP-18 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 358K |
| 代理商： | LTC1043MD883C |
LTC1043
5
1043fa
Test Circuit 1. Leakage Current Test
Common Mode Rejection Ratio (CMRR)
The LTC1043, when used as a differential to single-ended
converter rejects common mode signals and preserves
differential voltages (Figure 1). Unlike other techniques,
the LTC1043’s CMRR does not degrade with increasing
common mode voltage frequency. During the sampling
mode, the impedance of Pins 2, 3 (and 11, 12) should be
reasonably balanced, otherwise, common mode signals
will appear differentially. The value of the CMRR depends
on the value of the sampling and holding capacitors
(CS, CH) and on the sampling frequency. Since the
common mode voltages are not sampled, the
common mode signal frequency can well exceed the
sampling frequency without experiencing aliasing
phenomena. The CMRR of Figure 1 is measured by
TEST CIRCUITS
Test Circuit 2. RON Test
Test Circuit 3. Oscillator Frequency, fOSC
Test Circuit 4. CMRR Test
LTC1043 TC02
(7, 13, 6, 18)
(8, 14, 5, 15)
(11, 12, 2, 3)
100A to 1mA
CURRENT SOURCE
+
A
VIN
+
V+
LTC1043 TC03
4
V–
16
(TEST PIN)
IV
5
LTC1043
17
COSC
2
+
6
LTC1043 TC04
CMRR = 20 LOG
()
FOR OPTIMUM CMRR, THE COSC SHOULD
BE LARGER THAN 0.0047F, AND
THE SAMPLING CAPACITOR ACROSS
PINS 11 AND 12 SHOULD BE PLACED
OVER A SHIELD TIED TO PIN 10
+
V– ≤ VCM ≤ V
+
VCM
VOUT
13
14
12
11
10
78
1F
CAPACITORS ARE
NOT ELECTROLYTIC
NOTE:
+
APPLICATIO S I FOR ATIO
WU
UU
Figure 1. Differential to Single-Ended Converter
LTC1043 TC01
(7, 13, 6, 18)
(8, 14, 5, 15)
(11, 12, 2, 3)
NOTE: TO OPEN SWITCHES,
S1 AND S3
SHOULD BE CONNECTED
TO V–. TO OPEN S2, S4,
COSC PIN SHOULD BE
TO V+ COSC
+
A
0V TO 10V
LTC1043 AI01
CS, CH ARE MYLAR OR POLYSTRENE
+
CH
CS
C–
C+
VD
13
14
12
11
1/2 LTC1043
78
VD
VCM
+
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