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參數(shù)資料
| 型號(hào)： | LT685CN#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC COMP HI-SPD ECL OUTPUT 16-DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補(bǔ)充型，ECL |
| 電壓 - 輸入偏移（最小值）： | 2mV @ -5.2V，6V |
| 電流 - 輸入偏壓（最小值）： | 10µA @ -5.2V，6V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 22mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 80dB CMRR |
| 傳輸延遲（最大）： | 6.5ns |
| 工作溫度： | -30°C ~ 85°C |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 安裝類型： | 通孔 |
| 包裝： | 管件 |
4
685fa
LT685
LT685C
LT685M
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPD
Propagation Delay
TA = 25°C
4.5
5.5
6.5
4.5
5.5
6.5
ns
(Note 4)
TA = TMAX
5.0
9.5
5.5
12
ns
TA = TMIN
4.0
6.5
3.5
6.5
ns
tPD(E)
Latch Enable to
TA = 25°C
4.5
5.5
6.5
4.5
5.5
6.5
ns
Output Delay
TA = TMAX
5.0
9.5
5.5
12
ns
(Note 3)
TA = TMIN
4.0
6.5
3.5
6.5
ns
tS
Minimum Set-Up Time
TMIN ≤ TA ≤ 25°C
3.0
ns
(Note 3)
TA = TMAX
4.0
6.0
ns
tH
Minimum Hold Time
TMIN ≤ TA ≤ TMAX
1.0
ns
(Note 3)
tPW(E)
Minimum Latch Enable
TMIN ≤ TA ≤ 25°C
3.0
ns
Pulse Width (Note 3)
TA = TMAX
4.0
5.0
ns
(VIN = 100mV step, 5mV overdrive)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: For the metal can package, derate at 6.8mW/°C for operation at
ambient temperatures above 100°C; for the hermetic dual-in-line package,
derate at 9mW/°C for operation at ambient temperatures above 105°C.
Note 3: Guaranteed by design, but not tested.
Note 4: Sample tested at 25°C only.
Definitions:
tPD: The propagation delay measured from the time the input signal
crosses the input offset voltage to the 50% point of the output transition.
tPD(E): The propagation delay measured from the 50% point of the latch
enable signal positive transition to the 50% point of the output transition.
tS: The minimum time before the negative transition of the latch enable
signal that an input signal change must be present in order to be acquired
and held at the outputs.
tH: The minimum time after the negative transition of the latch enable
signal that the input signal must remain unchanged in order to be acquired
and held at the outputs.
tPW (E): The minimum time that the latch enable signal must be HIGH in
order to acquire and hold an input signal change.
SWITCHI G CHARACTERISTICS
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