參數(shù)資料
型號: LT6604CUFF-10#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC34
封裝: 4 X 7 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-34
文件頁數(shù): 14/16頁
文件大?。?/td> 198K
代理商: LT6604CUFF-10#PBF
LT6604-10
7
660410fb
PIN FUNCTIONS
+INA and –INA (Pins 2, 4): Channel A Input Pins. Signals
can be applied to either or both input pins through identi-
cal external resistors, RIN. The DC gain from differential
inputs to the differential outputs is 402Ω/RIN.
VOCMA (Pin 6): DC Common Mode Reference Voltage
for the 2nd Filter Stage in Channel A. Its value programs
the common mode voltage of the differential output of
the lter. Pin 6 is a high impedance input, which can be
driven from an external voltage reference, or Pin 6 can be
tied to Pin 34 on the PC board. Pin 6 should be bypassed
with a 0.01μF ceramic capacitor unless it is connected to
a ground plane.
V(Pins 7, 24, 31, 32, 35):
Negative Power Supply Pin
(can be ground).
VMIDB (Pin 8): The VMIDB pin is internally biased at midsup-
ply, see the Block Diagram. For single supply operation
the VMIDB pin should be bypassed with a quality 0.01μF
ceramic capacitor to ground. For dual supply operation,
Pin 8 can be bypassed or connected to a high quality DC
ground. A ground plane should be used. A poor ground
will increase noise and distortion. Pin 8 sets the output
common mode voltage of the 1st lter stage in channel B.
It has a 5.5kΩ impedance, and it can be overridden with
an external low impedance voltage source.
+INB and –INB (Pins 10, 12): Channel B Input Pins. Signals
can be applied to either or both input pins through identi-
cal external resistors, RIN. The DC gain from differential
inputs to the differential outputs is 402Ω/RIN.
VOCMB (Pin 14): DC Common Mode Reference Voltage
for the 2nd Filter Stage in Channel B. Its value programs
the common mode voltage of the differential output of
the lter. Pin 14 is a high impedance input, which can
be driven from an external voltage reference, or Pin 14
can be tied to Pin 8 on the PC board. Pin 14 should be
bypassed with a 0.01μF ceramic capacitor unless it is
connected to a ground plane.
V+A and V+B (Pins 25, 17):
Positive Power Supply Pins for
Channels A and B. For a single 3.3V or 5V supply (Pins 7,
24, 31, 32 and 35 grounded) a quality 0.1μF ceramic
bypass capacitor is required from the positive supply pin
(Pins 25, 17) to the negative supply pin (Pins 7, 24, 31,
32 and 35). The bypass should be as close as possible to
the IC. For dual supply applications, bypass the negative
supply pins to ground and Pins 25 and 17 to ground with
a quality 0.1μF ceramic capacitor.
+OUTB and –OUTB (Pins 19, 21): Output Pins. Pins 19 and
21 are the lter differential outputs for channel B. With a
typical short-circuit current limit greater than ±40mA, each
pin can drive a 100Ω and/or 50pF load to AC ground.
+OUTA and –OUTA (Pins 27, 29): Output Pins. Pins 27 and
29 are the lter differential outputs for channel A. With a
typical short-circuit current limit greater than ±40mA, each
pin can drive a 100Ω and/or 50pF load to AC ground.
VMIDA (Pin 34): The VMIDA pin is internally biased at mid-
supply, see the Block Diagram. For single supply operation
the VMIDA pin should be bypassed with a quality 0.01μF
ceramic capacitor to ground. For dual supply operation,
Pin 34 can be bypassed or connected to a high quality DC
ground. A ground plane should be used. A poor ground
will increase noise and distortion. Pin 34 sets the output
common mode voltage of the 1st lter stage in channel A.
It has a 5.5kΩ impedance, and it can be overridden with
an external low impedance voltage source.
Exposed Pad (Pin 35): V. The exposed pad must be
soldered to the PCB.
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