PIN FUNCTIONS (DFN/S8) IN
參數(shù)資料
型號: LT6600IDF-10#PBF
廠商: Linear Technology
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC AMP DIFF LN 12-DFN
標準包裝: 91
放大器類型: 差分
電路數(shù): 1
輸出類型: 差分
電流 - 輸入偏壓: 40µA
電壓 - 輸入偏移: 8000µV
電流 - 電源: 36mA
電壓 - 電源,單路/雙路(±): 3 V ~ 11 V,±1.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WFDFN 裸露焊盤
供應商設備封裝: 12-DFN-EP(4x4)
包裝: 管件
LT6600-10
7
66001fe
PIN FUNCTIONS (DFN/S8)
INand IN+ (Pins 1, 12/Pins 1, 8): Input Pins. Signals can
be applied to either or both input pins through identical
external resistors, RIN. The DC gain from differential inputs
to the differential outputs is 1580Ω/RIN.
NC (Pin 2, 5, 11/NA): No Connection.
VOCM (Pin 3/Pin 2): Is the DC Common Mode Reference
Voltage for the 2nd Filter Stage. Its value programs the
common mode voltage of the differential output of the lter.
This is a high impedance input, which can be driven from
an external voltage reference, or can be tied to VMID on the
PC board. VOCM should be bypassed with a 0.01μF ceramic
capacitor unless it is connected to a ground plane.
V+ and V (Pins 4, 8, 9/Pins 3, 6):
Power Supply Pins. For
a single 3.3V or 5V supply (Vgrounded) a quality 0.1μF
ceramic bypass capacitor is required from the positive
supply pin (V+) to the negative supply pin (V). The bypass
should be as close as possible to the IC. For dual supply
applications, bypass V+ to ground and Vto ground with
a quality 0.1μF ceramic capacitor.
OUT+ and OUT(Pins 6, 7/Pins 4, 5):
Output Pins. These
are the lter differential outputs. Each pin can drive a 100Ω
and/or 50pF load to AC ground.
VMID (Pin 10/Pin 7): The VMID pin is internally biased
at mid-supply, see block diagram. For single-supply
operation the VMID pin should be bypassed with a quality
0.01μF ceramic capacitor to V. For dual supply operation,
VMID can be bypassed or connected to a high quality DC
ground. A ground plane should be used. A poor ground
will increase noise and distortion. VMID sets the output
common mode voltage of the 1st stage of the lter. It has
a 5.5kΩ impedance, and it can be overridden with an
external low impedance voltage source.
BLOCK DIAGRAM
+ –
+
VOCM
+
VOCM
402Ω
200Ω
V+
V
11k
OP AMP
PROPRIETARY
LOWPASS
FILTER STAGE
VIN
VIN
+
RIN
6600 BD
IN+
VOCM
V+
OUT+
OUT
V
VMID
IN
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