INand IN+
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      參數(shù)資料
      型號(hào): LT6600CDF-2.5#TRPBF
      廠商: Linear Technology
      文件頁(yè)數(shù): 14/16頁(yè)
      文件大小: 0K
      描述: IC AMP DIFF LN 12-DFN
      標(biāo)準(zhǔn)包裝: 2,500
      放大器類型: 差分
      電路數(shù): 1
      輸出類型: 差分
      電流 - 輸入偏壓: 15µA
      電壓 - 輸入偏移: 5000µV
      電流 - 電源: 28mA
      電壓 - 電源,單路/雙路(±): 3 V ~ 11 V,±1.5 V ~ 5.5 V
      工作溫度: 0°C ~ 70°C
      安裝類型: 表面貼裝
      封裝/外殼: 12-WFDFN 裸露焊盤
      供應(yīng)商設(shè)備封裝: 12-DFN-EP(4x4)
      包裝: 帶卷 (TR)
      LT6600-2.5
      7
      660025fe
      PIN FUNCTIONS
      INand IN+ (Pins 1, 12/Pins 1, 8): Input Pins. Signals can
      be applied to either or both input pins through identical
      external resistors, RIN. The DC gain from differential inputs
      to the differential outputs is 1580Ω/RIN.
      NC (Pins 2, 5, 11/NA): No Connection
      VOCM (Pin 3/Pin 2): DC Common Mode Reference Voltage-
      for the 2nd Filter Stage. Its value programs the common
      mode voltage of the differential output of the lter. This
      is a high impedance input, which can be driven from an
      external voltage reference, or it can be tied to VMID on the
      PC board. VOCM should be bypassed with a 0.01μF ceramic
      capacitor unless it is connected to a ground plane.
      V+ and V(Pins 4, 8, 9/Pins 3, 6):
      Power Supply Pins. For
      a single 3.3V or 5V supply (Vgrounded) a quality 0.1μF
      ceramic bypass capacitor is required from the positive
      supply pin (V+) to the negative supply pin (V). The bypass
      should be as close as possible to the IC. For dual supply
      applications, bypass V+ to ground and Vto ground with
      a quality 0.1μF ceramic capacitor.
      OUT+ and OUT(Pins 6, 7/Pins 4, 5):
      Output Pins. These
      are the lter differential outputs. Each pin can drive a 100Ω
      and/or 50pF load to AC ground.
      VMID (Pin 10/Pin 7): The VMID pin is internally biased at
      mid-supply, see Block Diagram. For single supply op-
      eration, the VMID pin should be bypassed with a quality
      0.01μF ceramic capacitor to V. For dual supply operation,
      VMID can be bypassed or connected to a high quality DC
      ground. A ground plane should be used. A poor ground
      will increase noise and distortion. VMID sets the output
      common mode voltage of the 1st stage of the lter. It has
      a 5.5kΩ impedance, and it can be overridden with an
      external low impedance voltage source.
      (DFN/SO)
      BLOCK DIAGRAM
      + –
      +
      VOCM
      +
      VOCM
      1580Ω
      800Ω
      V+
      V
      11k
      OP AMP
      PROPRIETARY
      LOWPASS
      FILTER STAGE
      VIN
      VIN
      +
      RIN
      660025 BD
      IN+
      VOCM
      V+
      OUT+
      OUT
      V
      VMID
      IN
      相關(guān)PDF資料
      PDF描述
      TLW-113-05-G-D CONN HEADER .100" 26POS DL GOLD
      LT6600CDF-10#TRPBF IC AMP DIFF LN 12-DFN
      SSW-135-02-G-S CONN RCPT .100" 35POS SNGL GOLD
      TSW-145-26-G-S CONN HEADER 45POS .100" SGL GOLD
      SSW-136-02-G-S CONN RCPT .100" 36POS SNGL GOLD
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