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參數(shù)資料
| 型號： | LT6411CUD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DRVR/GAIN AMP DUAL 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 3300 V/µs |
| -3db帶寬： | 650MHz |
| 電流 - 輸入偏壓： | 17µA |
| 電壓 - 輸入偏移： | 3000µV |
| 電流 - 電源： | 8mA |
| 電流 - 輸出 / 通道： | 105mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 12 V，±2.25 V ~ 6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN-EP（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1322 (CN2011-ZH PDF) |
LT6411
9
6411f
APPLICATIONS INFORMATION
Power Supplies
The LT6411 can be operated on as little as ±2.25V or a
single 4.5V supply and as much as ±6V or a single 12V
supply. Internally, each supply is independent to improve
channel isolation. Note that the Exposed Pad is internally
connected to VEE and must not be grounded when using
split supplies. Do not leave any supply pins disconnected
or the part may not function correctly!
Enable/Shutdown
The LT6411 has a TTL compatible shutdown mode con-
trolled by the EN pin and referenced to the DGND pin. If
the amplier will be enabled at all times, the EN pin can
be connected directly to DGND. If the enable function is
desired, either driving the pin above 2V or allowing the
internal 46k pull-up resistor to pull the EN pin to the top
rail will disable the amplier. When disabled, the DC output
impedance will rise to approximately 740
Ω through the
internal feedback and gain resistors (assuming inputs at
ground). Supply current into the amplier in the disabled
state will be primarily through VCC and approximately
equal to (VCC – VEN)/46k.
It is important that the two following constraints on the
DGND pin and the EN pin are always followed:
VCC – VDGND ≥ 3V
–0.5V ≤ VEN – VDGND ≤ 5.5V
Split supplies of ±3V to ±5.5V will satisfy these require-
ments with DGND connected to 0V.
In dual supply cases with VCC less than 3V, DGND should
be connected to a potential below ground such as VEE.
Since the EN pin is referenced to DGND, it may need to be
pulled below ground in those cases. In order to protect the
internal enable circuitry, the EN pin should not be forced
more than 0.5V below DGND.
In single supply applications above 5.5V, an additional
resistor may be needed from the EN pin to DGND if the
pin is ever allowed to oat. For example, on a 12V single
supply, a 33k resistor would protect the pin from oating
too high while still allowing the internal pull-up resistor
to disable the part.
The DGND pin should not be pulled above the EN pin since
doing so will turn on an ESD protection diode. If the EN
pin voltage is forced a diode drop below the DGND pin,
current should be limited to 10mA or less.
The enable/disable times of the LT6411 are fast when
driven with a logic input. Turn on (from 50% EN input to
50% output) typically occurs in less than 50ns. Turn off
is slower, but is less than 300ns.
Gain Selection
The gain of the internal ampliers of the LT6411 is cong-
ured by connecting the IN+ and IN– pins to the input signal
or ground in the combinations shown in Figure 1.
As shown in the Simplied Schematic, the IN– pins connect
to the internal gain resistor of each amplier, and therefore,
each pin can be congured independently. Floating the
IN– pins is not recommended as the parasitic capacitance
causes an AC gain of 2 at high frequencies, despite a DC
gain of +1. Both inputs are connected together in the gain
of +1 conguration to avoid this limitation.
+
–
+
–
+V
–V
LT6411
IN+
AV = +2
IN–
OUT+
OUT–
+
–
+
–
+V
–V
LT6411
IN+
AV = –1
IN–
OUT–
OUT+
6411 F01
+
–
+
–
+V
–V
LT6411
IN+
AV = +1
IN–
OUT+
OUT–
Figure 1. LT6411 Congured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies
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