IN+
參數(shù)資料
型號(hào): LT5554IUH#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 16/32頁(yè)
文件大小: 0K
描述: IC VGA DIG CONTROL 32-QFN
標(biāo)準(zhǔn)包裝: 2,500
應(yīng)用: 可變?cè)鲆妫╒GA)
電路數(shù): 1
-3db帶寬: 1GHz
電流 - 電源: 200mA
電壓 - 電源,單路/雙路(±): 4.75 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 帶卷 (TR)
LT5554
23
5554f
Figure 16. Single-Ended Transformer Test Board (Simplied Schematic)
IN+
IN
T1
1:1
ETC1-1-13
MACOM
J1
50
J3
50
C5
1μF
LT5554
1, 3, 5, 7
9
5554 F16
OUT+
OUT
C9
0.1μF
C3
0.1μF
R6
68.1Ω
R5
68.1Ω
RO
400Ω
RIN
50Ω
RO
400Ω
VCC = 5V
VCCO = 5V
RLOAD
57.1Ω
OUTPUT
MATCHING
T2
TC2-1T
2:1
C18
0.1μF
C19
4.7μF
C8
0.1μF
C4
0.1μF
11
VCC VDEC
ENB
13
PG0
15
PG1
17
PG2
19
PG3
21
PG4
23
PG5
25
PG6
27
STROBE
29
VPG
31
MODE
33, 35, 37, 38
2, 4, ...40
J5, 40 PINS
SMT-TB
VCCO
R20
10k
PG1
R21
10k
PG2
R22
10k
PG3
R23
10k
PG4
R24
10k
PG5
R25
10k
PG6
R26
10k
ROUT = 50Ω
APPLICATIONS INFORMATION
Layout Considerations
Attention must be paid to the printed circuit board layout
to avoid output pin to input pin signal coupling (external
feedback). The evaluation board layout is a good example.
The exposed backside pad on the LT5554 package must be
soldered to PCB ground plane for thermal considerations.
Characterization Test Circuits
The LT5554’s typical performance data are on the test
circuits shown in Figures 16, 17 and 18 which are simpli-
ed schematics of the evaluation board schematic from
Figure 21.
The transformer board from Figure 16 was used for char-
acterization as a function of ROUT. For each ROUT option,
The T2 transformer model and the matching resistors R5,
R6 values are given in Table 3. The T2 transformer total
matching resistance is RMATCH = RO || (R5 + R6) (part
LT5554 internal, and part on board R5 and R6).
Table 3. Transformer Board ROUT Options
ROUT (Ω)
50
75
100
T2 (Mini-Circuits)
TC2-1T
TC3-1T
TC4-1W
NLOAD Ratio
234
RLOAD (Ω)
57.1
92.3
133.3
R5, R6 (Ω)
68.1
124
205
GP_BOARD (dB)
13.2
16
17.2
IL(T2) at
200MHz (dB)
–0.6
–0.65
–1
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