參數(shù)資料
型號: LT3957IUHE#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PQCC36
封裝: 5 X 6 MM, LEAD FREE, PLASTIC, QFN-36
文件頁數(shù): 14/28頁
文件大?。?/td> 359K
代理商: LT3957IUHE#PBF
LT3957
21
3957f
APPLICATIONS INFORMATION
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty cycle
of the main switch can be calculated based on the negative
output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX)occurswhentheconverter
has the minimum input voltage:
DMAX =
VOUT VD
VOUT VD VIN(MIN)
Inverting Converter: Output Diode and Input Capacitor
Selections
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those
of the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, yback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current owing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 owing through the
ESR and bulk capacitance of the output capacitor:
ΔVOUT(P–P) =ΔIL2 ESRCOUT +
1
8 COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufcient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 ΔIL2
Inverting Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor
(CDC, as shown in Figure 10) should be larger than the
maximum input voltage minus the output voltage (nega-
tive voltage):
VCDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO ows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX)
DMAX
1DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Board Layout
The high power and high speed operation of the LT3957
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3957 at high input voltages,
high switching frequencies, and high internal power switch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
tom of the package are SGND and SW terminals of the IC,
and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into the copper planes with as much as
area as possible.
To prevent radiation and high frequency resonance
problems, proper layout of the components connected
to the IC is essential, especially the power paths with
higher di/dt. The following high di/dt loops of different
topologies should be kept as tight as possible to reduce
inductive ringing:
In boost conguration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
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