參數(shù)資料
型號(hào)： LT3692EUH#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： 5.8 A DUAL SWITCHING CONTROLLER, 2750 kHz SWITCHING FREQ-MAX, PQCC32
封裝： 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32
文件頁(yè)數(shù)： 35/36頁(yè)
文件大?。?/td> 526K
代理商： LT3692EUH#PBF
LT3692
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3692f
PIN FUNCTIONS
BST1/2: The BST pin provides a higher than VIN base
drive to the power NPN to ensure a low switch drop. If the
voltage between the BST pin and the VIN pin is less than
the voltage required to fully turn on the power NPN, the
power switch is turned off to recharge the BST capacitor.
CMPI1/2: The CMPI pin is an input to a comparator with a
threshold of 720mV and 60mv of hysteresis. Connecting
the CMPI pin to the FB pin will generate a power good
signal when the output is within90% ofits regulated value.
CMPO1/2: The CMPO pin is an open-collector output that
sinks current when the CMPI pin falls below its threshold.
For a typical input voltage above 2.8V, its output state re-
mains true, although during shutdown, VIN1 undervoltage
lockout or thermal shutdown, its current sink capability is
reduced. The COMPO pins can be left open circuit or tied
together to form a single power good signal.
DIV:ThevoltagepresentattheDIVpindeterminestheratio
of channel 1 frequency to the master clock frequency set
by the RT/SYNC pin. The DIV pin is driven by an internal
current source with a typical value of 12A which allows
a single resistor from the DIV pin to ground to set the
DIV voltage and resulting channel 1 frequency divider.
Ratios of 1, 2, 4 and 8 are available. See the Applications
Information section for more information.
DNC: Do Not Connect.
GND: The exposed pad pin is the only ground connec-
tion for the device. The exposed pad should be soldered
to a large copper area to reduce thermal resistance. The
GND pin is common to both channels and also serves as
small-signal ground. For ideal operation all small-signal
ground paths should connect to the GND pin at a single
point avoiding any high current ground returns.
FB1/2:TheFBpinisthenegativeinputtotheerroramplifier.
The output switches to regulate this pin to 806mV with
respect to the exposed ground pad. Bias current flows
out of the FB pin.
ILIM1/2: The voltage present at the ILIM pin determines
the peak inductor current for the channel. The ILIM pin is
driven by an internal current source with a typical value
of 12A. A resistor from the ILIM pin to ground sets the
ILIM voltage. The maximum current limit range is 4.8A to
2A when the ILIM voltages are 1.5V and 0V respectively.
IND1/2:TheINDpinistheinputtotheinternalsenseresistor
that measures current flowing in the inductor. When the
current in the resistor exceeds the current dictated by the
VC pin, the SW latch is held in reset, disabling the output
switch. Bias current flows out of the IND pin.
RT/SYNC: The voltage present at the RT/SYNC pin deter-
mines the constant switching frequency. The RT/SYNC
pin is driven by an internal current source with a typical
value of 12A which allows a single resistor from the RT/
SYNC pin to ground to set the RT/SYNC voltage and result-
ing switching frequency. Minimum switching frequency
is typically 110kHz when VRT/SYNC is 0V and maximum
switching frequency is typically 2.5MHz when VRT/SYNC
is above 950mV.
Driving the RT/SYNC pin with an external clock signal will
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
theclocksignalisdetected.Eachrisingclockedgeinitiates
an oscillator ramp reset. A gain control loop servos the
oscillator charging current to maintain constant oscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode after
thesynchronizationdetectioncircuitrytimesout.Theclock
source impedance should be set such that the current out
oftheRT/SYNCpininresistormodegeneratesafrequency
roughly equivalent to the synchronization frequency. See
theApplicationsInformationsectionformoreinformation.
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