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參數(shù)資料
| 型號： | LT3688IFE#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO24 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 415K |
| 代理商： | LT3688IFE#PBF |
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LT3688
8
3688f
RT (Pin 1/Pin 22): The RT pin is used to set the internal
oscillator frequency. Tie a resistor from RT to GND to set
the switching frequency.
SYNC (Pin 2/Pin 23): Drive the SYNC pin with a logic-
level signal with positive and negative pulse widths of at
least 150ns. Do not oat this pin. Tie to GND if the SYNC
feature is not used.
EN/UVLO (Pin 3/Pin 24): The EN/UVLO pin is used to put
the LT3688 in shutdown mode. Pull the pin below 0.3V to
shut down the LT3688. The 1.25V threshold can function
as an accurate undervoltage lockout (UVLO), preventing
the regulator from operating until the input voltage has
reached the programmed level.
FB1, FB2 (Pins 4, 15/Pins 1, 12): The LT3688 regulates
the feedback pins to 0.800V. Connect the feedback resistor
divider taps to this pin.
RUN/SS1, RUN/SS2 (Pins 5, 14/Pins 2, 11): Place a
capacitor from RUN/SS to GND to program the soft start
period. Use a 1000pF or larger capacitor at these pins. To
ensure the SS capacitors are discharged, internal circuitry
pulls the RUN/SS pins low and disables switching during
startup before initiating the soft-start sequence. Once
the RUN/SS pins fall below 0.2V, the pull down turns off,
the SS capacitors start charging again, and switching is
enabled. Do not drive these pins directly. Use an open
drain or collector to pull them low, if necessary.
BST1, BST2 (Pins 6, 13/Pins 3, 10): The BST pins are
used to provide drive voltage, higher than the input volt-
age, to the internal NPN power switches.
SW1, SW2 (Pins 7, 12/Pins 4, 9): The SW pins are the
outputs of the internal power switches. Connect these
pins to the inductors, catch diodes and boost capacitors.
DA1, DA2 (Pins 8, 11/Pins 5, 8): Tie the DA pin to the
anode of the external catch Schottky diode. If the DA pin
current exceeds 1.2A, which could occur in an overload
or short-circuit condition, switching is disabled until the
DA pin current falls below 1.2A.
VIN (Pin 9/Pin 6): The VIN pin supplies current to the
LT3688’s internal circuitry and to the internal power
switches and must be locally bypassed.
PIN FUNCTIONS
CONFIG (Pin 10/Pin 7): The CONFIG pin programs the
start-up sequence of the two voltage regulators and the
behavior of the power-on reset and watchdog timers. To
select one of three conguration options, tie the CONFIG pin
to VIN, tie the CONFIG pin to GND or leave the CONFIG pin
oating. With the CONFIG pin tied to VIN, each reset output
depends on its respective FB pin. Channel 2 only starts when
FB1 rises above 0.72V, and the watchdog timer only starts
when both RST pins go high. With the CONFIG pin tied to
GND, both RST pins pull low until both FB pins rise above
0.72V and the POR timer programmed by CPOR1 expires.
Again, channel 2 only starts when FB1 rises above 0.72V,
and the watchdog timer only starts when both RST pins go
high. Tie CPOR2 to GND if the CONFIG pin is tied low. With
the CONFIG pin oating, both channels start coincidentally,
each reset output depends on its respective FB pin, and the
watchdog timer starts when RST1 goes high.
RST1, RST2 (Pins 17, 16/Pins 14, 13): The RST pins are
active low, open-drain logic outputs with a weak pull-up to
BIAS.AfterVFBrisesabove0.72V,theresetremainsasserted
for the period set by the capacitor on the CPOR pin. Tie the
RSTpinstoBIASwitha100kresistorforastrongerpull-up.
WDO (Pin 18/Pin 15): WDO will go low if the micropro-
cessor fails to drive the WDI pin of the LT3688 with the
appropriate signal. Tie the WDO pin to BIAS with a 100k
resistor for a stronger pull-up. Keep capacitive loading on
this pin below 1000pF.
WDE (Pin 19/Pin 16): The watchdog timer enable pin
disables the watchdog timer if the WDE voltage exceeds
1V. Float this pin or tie to ground for normal operation.
WDI (Pin 20/Pin 17): The watchdog timer input pin
receives the watchdog signal from the microprocessor.
If two or more negative edges occur on WDI before the
programmed fast timer period or no negative edge occurs
within the slow timer period, the part will pulse WDO low
with a pulse width of 1/8th of the slow timer period. Drive
the WDI pin with a pulse width of at least 300ns.
BIAS (Pin 22/Pin 19): The BIAS pin supplies current to the
internal circuitry when BIAS is above 3V, helping reduce
input quiescent current. The internal Schottky diodes are
connected from BIAS to BST, providing the charging path
for the boost capacitors.
(QFN/TSSOP)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LT3688IUF#PBF | 功能描述:IC REG BUCK ADJ 0.8A DL 24QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 產(chǎn)品培訓(xùn)模塊:MIC23xxx HyperLight Load™ Regulators 標(biāo)準(zhǔn)包裝:5,000 系列:HyperLight Load® 類型:降壓（降壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:1.8V 輸入電壓:2.7 V ~ 5.5 V PWM 型:混合物 頻率 - 開關(guān):4MHz 電流 - 輸出:2A 同步整流器:是 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-VFDFN 裸露焊盤，8-MLF? 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:8-MLF?（2x2） 產(chǎn)品目錄頁面:1094 (CN2011-ZH PDF) 其它名稱:576-3303-2 |
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| LT3689-5 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
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