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參數(shù)資料
| 型號： | LT3681EDE |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 4.4 A SWITCHING REGULATOR, 3100 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | 4 X 3 MM, PLASTIC, DFN-14 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 367K |
| 代理商： | LT3681EDE |
LT3681
15
3681f
Soft-Start
The RUN/SS pin can be used to soft-start the LT3681,
reducing the maximum input current during start-up.
The RUN/SS pin is driven through an external RC lter to
create a voltage ramp at this pin. Figure 7 shows the start-
up and shut-down waveforms with the soft-start circuit.
By choosing a large RC time constant, the peak start-up
current can be reduced to the current that is required to
regulate the output, with no overshoot. Choose the value
of the resistor so that it can supply 20A when the RUN/SS
pin reaches 2.3V.
Synchronization
The internal oscillator of the LT3681 can be synchronized
to an external 275kHz to 475kHz clock by using a 5pF
to 20pF capacitor to connect the clock signal to the RT
pin. The resistor tying the RT pin to ground should be
chosen such that the LT3681 oscillates 20% lower than
the intended synchronization frequency (see Setting the
Switching Frequency section).
The LT3681 should not be synchronized until its output
is near regulation as indicated by the PG ag. This can be
done with the system microcontroller/microprocessor or
with a discrete circuit by using the PG output. If a sync
signal is applied while the PG is low, the LT3681 may
exhibit erratic operation.
When applying a sync signal, positive clock transitions
reset LT3681’s internal clock and negative transitions
initiate a switch cycle. The amplitude of the sync signal
must be at least 2V. The sync signal duty cycle can range
from 5% up to a maximum value given by the following
equation:
DC
VV
V
f
SYNC MAX
OUT
D
IN
SW
D
SW
() =
+
16
–
– 0
00ns
where VOUT is the programmed output voltage, VD is the
diode forward drop, VIN is the typical input voltage, VSW
is the switch drop, and fSW is the desired switching fre-
quency. For example, a 24V input to 5V output at 300kHz
can be synchronized to a square wave with a maximum
duty cycle of 60%. For some applications, such as 12VIN
to 5VOUT at 350kHz, the maximum allowable sync duty
cycle will be less than 50%. If a low duty cycle clock cannot
be obtained from the system, then a one-shot should be
used between the sync signal and the LT3681. The value
of the coupling capacitor which connects the clock signal
to the RT pin should be chosen based on the clock signal
amplitude. Good starting values for 3.3V and 5V clock
signals are 10pF and 5pF, respectively. These values should
be tested and adjusted for each individual application to
assure reliable operation.
Figure 6. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
LOAD CURRENT (A)
0.001
INPUT
VOL
TAGE
(V)
4.0
4.5
5.0
10
3.5
3.0
2.0
0.01
0.1
1
2.5
6.0
5.5
3681 F06
LOAD CURRENT (A)
0.001
INPUT
VOL
TAGE
(V)
5.0
4.5
6.0
5.5
7.0
6.5
10
4.0
3.5
2.0
0.01
0.1
1
3.0
2.5
8.0
7.5
VOUT = 3.3V
TA = 25°C
L = 4.7
m
f = 800 kHz
TO START (RUN/SS = VIN)
TO START (RUN/SS CONTROL)
TO RUN
TO START (RUN/SS = VIN)
TO START (RUN/SS CONTROL)
TO RUN
VOUT = 5.0V
TA = 25°C
L = 4.7
m
f = 800 kHz
Figure 7. To Soft-Start the LT3681, Add a Resistor
and Capacitor to the RUN/SS Pin
3681 F07
IL
1A/DIV
VRUN/SS
2V/DIV
VOUT
2V/DIV
RUN/SS
GND
0.22
F
RUN
15k
2ms/DIV
APPLICATIONS INFORMATION
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| LT3681EDE#PBF | 功能描述:IC REG BUCK ADJ 2A 14DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:降壓（降壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:1.2V 輸入電壓:2.05 V ~ 6 V PWM 型:電壓模式 頻率 - 開關(guān):2MHz 電流 - 輸出:500mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:6-UFDFN 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:6-SON（1.45x1） 產(chǎn)品目錄頁面:1032 (CN2011-ZH PDF) 其它名稱:296-25628-2 |
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| LT3682 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:42V, 750mA Step-Down Regulator with 2.5μA |
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