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參數(shù)資料
| 型號： | LT3587EUD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 395K |
| 代理商： | LT3587EUD#TRPBF |
LT3587
20
3587fc
APPLICATIONS INFORMATION
Figure 19. Recommended Component Placement
Figure 18. High Current Paths
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential.
In order to minimize magnetic eld radiation, reduce the
parasitic inductance by keeping the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. Figure 18 outlines the critical paths.
C6
C1
SW1
GND
VVIN
L1
Q1
CAP1
DS1
LT3587
C6
C4
SW3
GND
VVIN
L4
Q3
CAP3
DS3
LT3587
3587 F18
C6
C7
SW2
GND
VVIN
VNEG
L2
L3
Q2
DS2
LT3587
C2
The voltage signals of the SW1, SW2 and SW3 pins have
rise and fall times of a few ns. Minimize the length and area
of all traces connected to the SW1, SW2 and SW3 pins
to reduce capacitive coupling between these fast nodes
and other circuitry. In particular, keep all the traces of the
feedback voltage pins (FB1, FB2, VFB3 and IFB3) away from
the switching node. Always use a ground plane under the
switching regulator to minimize interplane coupling.
Finally, place as much of the output capacitors of each
channel close to their respective CAP pins. Recommended
component placement is shown in Figure 19.
3587 F19
L4
L3
L2
C7
C2
U1
L1
C1
C4
C6
(OPT)
C6
(OPT)
C6
(OPT)
DS2
DS1
RFB1
CFB1
C5
C6
C3
RIFB3
RFB2
CFB2
VNEG
VIN
CAP3
VIN
VOUT3
VOUT1
CAP1
VIN
DS3
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