參數(shù)資料
型號: LT3508EUF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3.2 A DUAL SWITCHING CONTROLLER, 1060 kHz SWITCHING FREQ-MAX, PQCC24
封裝: 4 X 4 MM, PLASTIC, MO-220WGGD-X, QFN-24
文件頁數(shù): 23/24頁
文件大?。?/td> 365K
代理商: LT3508EUF
LT3508
8
3508f
OPERATION
The LT3508 is a dual constant frequency, current mode
regulator with internal power switches. Operation can be
best understood by referring to the Block Diagram. If the
SHDN pin is tied to ground, the LT3508 is shut down and
draws minimal current from the input source tied to the
VIN pins. If the SHDN pin exceeds 1V, the internal bias
circuits turn on, including the internal regulator, reference
and oscillator. The switching regulators will only begin to
operate when the
SHDN pin exceeds 2.63V.
The switcher is a current mode regulator. Instead of directly
modulating the duty cycle of the power switch, the feedback
loop controls the peak current in the switch during each
cycle. Compared to voltage mode control, current mode
control improves loop dynamics and provides cycle-by-
cycle current limit. A pulse from the oscillator sets the
RS ip-op and turns on the internal NPN power switch.
Current in the switch and the external inductor begins to
increase. When this current exceeds a level determined
by the voltage at VC, current comparator C1 resets the
ip-op, turning off the switch. The current in the inductor
ows through the external Schottky diode and begins to
decrease. The cycle begins again at the next pulse from the
oscillator. In this way, the voltage on the VC pin controls
the current through the inductor to the output. The internal
error amplier regulates the output current by continually
adjusting the VC pin voltage. The threshold for switching
on the VC pin is 0.8V, and an active clamp of 1.75V limits
the output current.
The switching frequency is set either by the resistance to
GND at the RT/SYNC pin or the frequency of the logic-level
signal driving the RT/SYNCpin.Adetectioncircuitmonitors
for the presence of a SYNC signal on the pin and switches
between the two modes. Unique circuitry generates the
appropriate slope compensation ramps and generates the
180° out-of-phase clocks for the two channels.
The switching regulator performs frequency foldback
during overload conditions. An amplier senses when VFB
is less than 0.625V and begins decreasing the oscillator
frequency down from full frequency to 12% of the nominal
frequency when VFB = 0V. The FB pin is less than 0.8V
during start-up, short-circuit and overload conditions.
Frequency foldback helps limit switch current under these
conditions.
The switch driver operates either from VIN or from the
BOOST pin. An external capacitor and Schottky diode
are used to generate a voltage at the BOOST pin that is
higher than the input supply. This allows the driver to
saturate the internal bipolar NPN power switch for ef-
cient operation.
The TRACK/SS pin serves as an alternative input to the
error amplier. The amplier will use the lowest voltage
of either the reference of 0.8V or the voltage on the
TRACK/SS pin as the positive input of error amplier.
Since the TRACK/SS pin is driven by a constant current
source, a single capacitor on the pin will generate a linear
ramp on the output voltage. Tying the TRACK/SS pin to a
resistor divider from the output of one of the switching
regulators allows one output to track another.
The PG output is an open-collector transistor that is off
when the output is in regulation, allowing an external
resistor to pull the PG pin high. Power good is valid when
the LT3508 is enabled (
SHDN is high) and V
IN1 is greater
than ~2.4V.
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