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參數資料
| 型號： | LT3494EDDB#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.25 A SWITCHING REGULATOR, PDSO8 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-8 |
| 文件頁數： | 9/12頁 |
| 文件大?。?/td> | 261K |
| 代理商： | LT3494EDDB#PBF |
LT3494/LT3494A
6
3494fb
BLOCK DIAGRAM
PIN FUNCTIONS
SW (Pin 1): Switch Pin. This is the collector of the internal
NPN power switch. Minimize the metal trace area connected
to this pin to minimize EMI.
GND (Pin 2): Ground. Tie directly to local ground plane.
VCC (Pin 3): Input Supply Pin. Must be locally
bypassed.
CTRL (Pin 4): Dimming Pin. If not used, tie CTRL to 1.5V
or higher. If in use, drive CTRL below 1.225V to override
the internal reference. See Applications Information for
more information.
SHDN (Pin 5): Shutdown Pin. Tie to 1.5V or more to
enable device. Ground to shut down.
FB (Pin 6): Feedback Pin. Reference voltage is 1.225V.
There is an internal 182k resistor from the FB pin to GND.
To achieve the desired output voltage, choose R1 accord-
ing to the following formula:
R
V
k
OUT MAX
1 182
1 225
1
=
.
–
()
Ω
VOUT (Pin 7): Drain of Output Disconnect PMOS. Place a
bypass capacitor from this pin to GND. See Applications
Information.
CAP (Pin 8): This is the cathode of the internal Schottky
diode. Place a bypass capacitor from this pin to GND.
Exposed Pad (Pin 9): Ground. This pin must be soldered
to PCB.
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