VOSH Input Offset Voltage Hystere" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LT1990ACS8
寤犲晢锛� Linear Technology
鏂囦欢闋佹暩(sh霉)锛� 16/16闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AMP DIFF +/-250V MCRPWR 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 100
鏀惧ぇ鍣ㄩ鍨嬶細 宸垎
闆昏矾鏁�(sh霉)锛� 1
杓稿嚭椤炲瀷锛� 婊挎摵骞�
杞�(zhu菐n)鎻涢€熺巼锛� 0.55 V/µs
-3db甯跺锛� 105kHz
闆诲 - 杓稿叆鍋忕Щ锛� 900µV
闆绘祦 - 闆绘簮锛� 140µA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 22mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 2.7 V ~ 36 V锛�±1.35 V ~ 18 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SO
鍖呰锛� 绠′欢
LT1990
9
1990fb
LT1990H
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOSH
Input Offset Voltage Hysteresis, RTI
(Note 11)
鈼�
250
V
PSRR
Power Supply Rejection Ratio, RTI
VS = 卤1.35V to 卤18V
鈼�
77
dB
Minimum Supply Voltage
Guaranteed by PSRR
鈼�
卤1.35
V
IS
Supply Current
鈼�
330
A
VOUT
Output Voltage Swing
鈼�
卤14.2
V
ISC
Output Short-Circuit Current
Short to V鈥�
鈼�
1.5
mA
Short to V+
鈼�
7mA
SR
Slew Rate
G = 1, VOUT = 卤10V
鈼�
0.1
V/
s
卤15V ELECTRICAL CHARACTERISTICS
The
鈼� denotes the specifications which apply over the temperature range of 鈥�40
掳C 鈮� TA 鈮� 125掳C. VS = 卤15V, RL = 10k, VCM = VREF = 0V,
G = 1, 10, unless otherwise noted. (Notes 4, 6)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ESD (Electrostatic Discharge) sensitive device. Extensive use of
ESD protection devices are used internal to the LT1990, however, high
electrostatic discharge can damage or degrade the device. Use proper ESD
handling precautions.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT1990C/LT1990I are guaranteed functional over the
operating temperature range of 鈥� 40
掳C to 85掳C. The LT1990H is
guaranteed functional over the operating temperature range of 鈥�40
掳C
to 125
掳C.
Note 5: The LT1990C is guaranteed to meet the specified performance
from 0
掳C to70掳C and is designed, characterized and expected to meet
specified performance from 鈥�40
掳C to 85掳C but is not tested or QA
sampled at these temperatures. The LT1990I is guaranteed to meet
specified performance from 鈥�40
掳C to 85掳C. The LT1990H is guaranteed to
meet specified performance from 鈥�40
掳C to 125掳C.
Note 6: G = 10 limits are guaranteed by correlation to G = 1 tests and gain
error tests at G = 10.
Note 7: Limits are guaranteed by correlation to 鈥�5V to 80V CMRR tests.
Note 8: VS = 3V limits are guaranteed by correlation to VS = 5V and
VS = 卤15V tests.
Note 9: VS = 5V limits are guaranteed by correlation to VS = 3V and
VS = 卤15V tests.
Note 10: This parameter is not 100% tested.
Note 11: Hysteresis in offset voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Offset voltage hysteresis is always measured at 25
掳C, but the
IC is cycled to 85
掳C I-grade (70掳C C-grade or 125掳C H-grade) or 鈥�40掳C
I/H-grade (0
掳C C-grade) before successive measurement.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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