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參數(shù)資料
| 型號： | LT1961IMS8E#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 154K |
| 代理商： | LT1961IMS8E#TR |
12
LT1961
1961fa
APPLICATIONS INFORMATION
WU
U
THERMAL CALCULATIONS
Power dissipation in the LT1961 chip comes from four
sources: switch DC loss, switch AC loss, drive current, and
input quiescent current. The following formulas show how
to calculate each of these losses. These formulas assume
continuous mode operation, so they should not be used
for calculating efficiency at light load currents.
DC duty cycle
VV
V
I
VI
V
OUT
IN
OUT
SW
OUT
IN
,
()
()(
)
=
=
Switch loss:
PDC I
R
n I
V
f
SW
OUT
=+
()( )( )
()(
) (
)
2
17
VIN loss:
P
VI
DC
mA V
VIN
IN
SW
IN
=+
()(
)(
)
()
50
1
RSW = Switch resistance (≈ 0.27Ω hot)
Example: VIN = 5V, VOUT = 12V and IOUT = 0.5A
Total power dissipation = 0.23 + 0.31 + 0.07 + 0.005 =
0.62W
Thermal resistance for LT1961 package is influenced by
the presence of internal or backside planes. With a full
plane under the package, thermal resistance will be about
50
°C/W. To calculate die temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
TJ = TA + θJA (PTOT)
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated,
with no device power, in an oven. The same measurement
can then be used in operation to indicate the die tempera-
ture.
FREQUENCY COMPENSATION
Loop frequency compensation is performed on the output
of the error amplifier (VC pin) with a series RC network.
The main pole is formed by the series capacitor and the
output impedance (
≈500kΩ) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a “zero” at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor, typi-
cally one-tenth the size of the main compensation capaci-
tor, is sometimes used to reduce the switching frequency
ripple on the VC pin. VC pin ripple is caused by output
voltage ripple attenuated by the output divider and multi-
plied by the error amplifier. Without the second capacitor,
VC pin ripple is:
VC Pin Ripple =
VRIPPLE = Output ripple (VP–P)
gm = Error amplifier transconductance
(
≈850μmho)
RC = Series resistor on VC pin
VOUT = DC output voltage
1.2(VRIPPLE)(gm)(RC)
(VOUT)
To prevent irregular switching, VC pin ripple should be
kept below 50mVP–P. Worst-case VC pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 47pF capacitor on the VC pin reduces switch-
ing frequency ripple to only a few millivolts. A low value for
RC will also reduce VC pin ripple, but loop phase margin
may be inadequate.
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