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參數(shù)資料
| 型號(hào)： | LT1959C |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| 中文描述： | 抗輻射高效，5安培開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 292K |
| 代理商： | LT1959C |
19
LT1959
APPLICATIO
S I
FOR
ATIO
U
W
U
U
Figure 10. Response from V
C
Pin to Output
FREQUENCY (Hz)
G
μ
M
P
3000
2500
2000
1500
1000
500
200
150
100
50
0
–50
100
10k
100k
10M
1595 F11
1k
1M
GAIN
PHASE
R
200k
C
12pF
V
C
ERROR AMPLIFIER EQUIVALENT CIRCUIT
R
LOAD
= 50
V
FB
2
×
10
–3
)
(
Figure 11. Error Amplifier Gain and Phase
Figure 12. Overall Loop Characteristics
What About a Resistor in the Compensation Network
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (R
C
) in series with the
compensation capacitor. Increasing the size of this resis-
tor generally creates better and better loop stability, but
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for R
C
may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for R
C
where gain margin falls to zero is:
R Loop
V
G
G
ESR
OUT
MP
MA
Gain =1
(
)
=
(
)(
)(
)
1 21
.
FREQUENCY (Hz)
G
C
P
C
40
20
0
–20
–40
40
0
–40
–80
–120
10
1k
10k
1M
1959 F10
100
100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V
I
OUT
= 2A
FREQUENCY (Hz)
L
L
80
60
40
20
0
–20
200
150
100
50
0
–50
10
1k
10k
1M
1595 F12
100
100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V, I
OUT
= 2A
C
OUT
= 100
μ
C
C
= 1.5nF, R
C
= 0, L = 10
μ
H
Error amplifier transconductance phase and gain are shown
in Figure 11. The error amplifier can be modeled as a
transconductance of 2000
μ
Mho, with an output imped-
ance of 200k
in parallel with 12pF. In all practical
applications, the compensation network from V
C
pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
This means that the error amplifier characteristics them-
selves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
tion network.
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 1.5nF, giving the
error amplifier a pole at 530Hz, with phase rolling off to 90
°
and staying there. The overall loop has a gain of 74dB at
low frequency, rolling off to unity-gain at 100kHz. Phase
shows a two-pole characteristic until the ESR of the output
capacitor brings it back above 10kHz. Phase margin is
about 60
°
at unity-gain.
Analog experts will note that around 4.4kHz, phase dips
very close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR willcause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
(
≥
±
3:1).
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| LT1959CR#PBF | 功能描述:IC REG BUCK ADJ 4.5A D2PAK RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:降壓（降壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:1.2V 輸入電壓:2.05 V ~ 6 V PWM 型:電壓模式 頻率 - 開關(guān):2MHz 電流 - 輸出:500mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:6-UFDFN 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:6-SON（1.45x1） 產(chǎn)品目錄頁面:1032 (CN2011-ZH PDF) 其它名稱:296-25628-2 |
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