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參數(shù)資料
| 型號： | LT1766HGN#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 228 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 284K |
| 代理商： | LT1766HGN#PBF |
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LT1766/LT1766-5
1766fb
APPLICATIO S I FOR ATIO
WU
UU
VC control voltage to the point where some sort of cycle-
skipping or odd/even cycle behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high VIN, low VOUT
and high fOSC can result in an unacceptably short
minimum switch on time. Cycle skipping and/or odd/
even cycle behavior will result although correct output
voltage is usually maintained.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the VC compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT1766 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1766 can be considered as two gm blocks, the error
amplifier and the power stage.
Figure 11 shows the overall loop response. At the VC pin,
the frequency compensation components used are:
RC = 2.2k, CC = 0.022F and CF = 220pF. The output
capacitor used is a 100
F, 10V tantalum capacitor with
typical ESR of 100m
.
The ESR of the tantalum output capacitor provides a useful
zero in the loop frequency response for maintaining stabil-
ity. This ESR, however, contributes significantly to the
ripple voltage at the output (see Output Ripple Voltage in
the Applications Section). It is possible to reduce capaci-
tor size and output ripple voltage by replacing the tantalum
output capacitor with a ceramic output capacitor because
of its very low ESR. The zero provided by the tantalum
output capacitor must now be reinserted back into the
loop. Alternatively there may be cases where, even with
the tantalum output capacitor, an additional zero is re-
quired in the loop to increase phase margin for improved
transient response.
A zero can be added into the loop by placing a resistor, RC,
at the VC pin in series with the compensation capacitor, CC
or by placing a capacitor, CFB, between the output and the
FB pin.
FREQUENCY (Hz)
GAIN
(dB)
80
60
40
20
0
–20
–40
PHASE
(DEG)
180
150
120
90
60
30
0
1766 F11
GAIN
PHASE
10
VIN = 42V
VOUT = 5V
ILOAD = 500mA
COUT = 100F, 10V, 0.1
1k
10k
1M
100
100k
RC = 2.2k
CC = 22nF
CF = 220pF
Figure 11. Overall Loop Response
–
+
1.22V
VSW
VC
LT1766
GND
1766 F10
R1
OUTPUT
ESR
CF
CC
RC
RO
200k
ERROR
AMPLIFIER
FB
R2
C1
RLOAD
CURRENT MODE
POWER STAGE
gm = 2mho
gm =
2000
mho
+
TANTALUM
CFB
CERAMIC
ESL
C1
Figure 10. Model for Loop Response
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