
LT1722/LT1723/LT1724
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SIMPLIFIED SCHEMATIC
APPLICATIONS INFORMATION
Power dissipation is composed of two parts. The rst is
due to the quiescent supply current and the second is due
to on-chip dissipation caused by the load current.
Worst-case instantaneous power dissipation for a given
resistive load in one amplier occurs at the maximum
supply current and when the output voltage is at half of
either supply voltage (or the maximum swing if less than
half supply voltage).
Therefore PD(MAX) in one amplier is:
PD(MAX) = (V+ – V–)(IS(MAX)) + (V+/2)2/RL
or
PD(MAX) = (V+ – V–)(IS(MAX)) +
(V+ – VO(MAX))(VO(MAX)/RL)
Example. Worst-case conditions are: both op amps in
the LT1723IS8 are at TA = 85°C, VS = ±5V, RL = 150Ω,
VOUT = 2.5V.
PD(MAX) = 2 [(10V)(5.95mA) + (2.5V)2/150Ω] = 203mW
TJ(MAX) = 85°C + (203mW)(190°C/W) = 124°C
which is less than the absolute maximum rating at 150°C.
Circuit Operation
The LT1722/LT1723/LT1724 circuit topology is a voltage
feedback amplier. The operation of the circuit can be
understood by referring to the Simplied Schematic. The
rst stage is a folded cascode formed by the transistors
Q1 through Q4. A degeneration resistor, R, is used in the
input stage. The current mirror Q5, Q6 is bootstrapped
by Q7. The capacitor, C, assures the bandwidth and the
slew rate performance. The output stage is formed by
complementary emitter followers, Q8 through Q11. The
diodes D1 and D2 protect against input reversed biasing.
The remaining part of the circuit assures optimum voltage
and current biases for all stages.
Low noise, reduced current supply, high speed and
DC accurate parameters are distinctive features of the
LT1722/LT1723/LT1724.
Q2
+IN
Q1
D1
D2
R
?–IN
R2
Q6
Q7
Q9
Q10
VS
+
VS
–
OUT
1723 SS
Q11
Q8
Q4
C
VBIAS
I3
I4
I5
I2
I1
R1
Q5
Q3