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    參數(shù)資料
    型號(hào): LT1720IDD#TRPBF
    廠商: Linear Technology
    文件頁(yè)數(shù): 28/28頁(yè)
    文件大?。?/td> 0K
    描述: IC COMPARATOR DUAL HS 3/5V 8-DFN
    標(biāo)準(zhǔn)包裝: 2,500
    系列: UltraFast™
    類(lèi)型: 通用
    元件數(shù): 2
    輸出類(lèi)型: CMOS,滿(mǎn)擺幅,TTL
    電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V
    電壓 - 輸入偏移(最小值): 3mV @ 5V
    電流 - 輸入偏壓(最小值): 6µA @ 5V
    電流 - 輸出(標(biāo)準(zhǔn)): 20mA
    電流 - 靜態(tài)(最大值): 7mA
    CMRR, PSRR(標(biāo)準(zhǔn)): 70dB CMRR,80dB PSRR
    傳輸延遲(最大): 10ns
    磁滯: 7mV
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 8-WFDFN 裸露焊盤(pán)
    安裝類(lèi)型: 表面貼裝
    包裝: 帶卷 (TR)
    LT1720/LT1721
    9
    17201fc
    High Speed Design Considerations
    Application of high speed comparators is often plagued
    by oscillations. The LT1720/LT1721 have 4mV of internal
    hysteresis, which will prevent oscillations as long as
    parasitic output to input feedback is kept below 4mV.
    However, with the 2V/ns slew rate of the LT1720/LT1721
    outputs, a 4mV step can be created at a 100Ω input source
    with only 0.02pF of output to input coupling. The pinouts
    of the LT1720/LT1721 have been arranged to minimize
    problems by placing the most sensitive inputs (invert-
    ing) away from the outputs, shielded by the power rails.
    The input and output traces of the circuit board should
    also be separated, and the requisite level of isolation is
    readily achieved if a topside ground plane runs between
    the outputs and the inputs. For multilayer boards where
    the ground plane is internal, a topside ground or supply
    trace should be run between the inputs and outputs, as
    illustrated in Figure 1.
    APPLICATIONS INFORMATION
    Although both VCC pins are electrically shorted internal to
    the LT1721, they must be shorted together externally as
    well in order for both to function as shields. The same is
    true for the two GND pins.
    The supply bypass should include an adjacent 10nF ce-
    ramic capacitor and a 2.2μF tantalum capacitor no farther
    than 5cm away; use more capacitance if driving more
    than 4mA loads. To prevent oscillations, it is helpful to
    balance the impedance at the inverting and noninverting
    inputs; source impedances should be kept low, preferably
    1kΩ or less.
    The outputs of the LT1720/LT1721 are capable of very
    high slew rates. To prevent overshoot, ringing and other
    problems with transmission line effects, keep the output
    traces shorter than 10cm, or be sure to terminate the lines
    to maintain signal integrity. The LT1720/LT1721 can drive
    DC terminations of 250Ω or more, but lower characteristic
    impedance traces can be driven with series termination
    or AC termination topologies.
    Hysteresis
    The LT1720/LT1721 include internal hysteresis, which
    makes them easier to use than many other comparable
    speed comparators.
    The input-output transfer characteristic is illustrated in
    Figure 2 showing the denitions of VOS and VHYST based
    upon the two measurable trip points. The hysteresis band
    makes the LT1720/LT1721 well behaved, even with slowly
    moving inputs.
    Figure 1. Typical Topside Metal for Multilayer PCB Layouts
    17201 F01
    (b)
    (a)
    Figure 1a shows a typical topside layout of the LT1720
    on such a multilayer board. Shown is the topside metal
    etch including traces, pin escape vias, and the land pads
    for an SO-8 LT1720 and its adjacent X7R 10nF bypass
    capacitor in a 1206 case.
    The ground trace from Pin 5 runs under the device up to
    the bypass capacitor, shielding the inputs from the out-
    puts. Note the use of a common via for the LT1720 and
    the bypass capacitor, which minimizes interference from
    high frequency energy running around the ground plane
    or power distribution traces.
    Figure 1b shows a typical topside layout of the LT1721
    on a multilayer board. In this case, the power and ground
    traces have been extended to the bottom of the device
    solely to act as high frequency shields between input and
    output traces.
    Figure 2. Hysteresis I/O Characteristics
    VHYST
    (= VTRIP
    + – VTRIP–)
    VHYST/2
    VOL
    17201 F02
    VOH
    VTRIP
    VTRIP
    +
    VIN = VIN
    + – VIN–
    VTRIP
    + + VTRIP–
    2
    VOS =
    V
    OUT
    0
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