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參數(shù)資料
| 型號： | LT1469IS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP 16BIT DUAL 90MHZ 8SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 22 V/µs |
| 增益帶寬積： | 90MHz |
| 電流 - 輸入偏壓： | 10nA |
| 電壓 - 輸入偏移： | 50µV |
| 電流 - 電源： | 4.1mA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
LT1469
11
1469fb
TYPICAL PERFORMANCE CHARACTERISTICS
Small-Signal Transient, AV = 1
Small-Signal Transient, AV = –1
Large-Signal Transient, AV = 1
Large-Signal Transient, AV = –1
Layout and Passive Components
The LT1469 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example, fast settling time) use a ground
plane, short lead lengths and RF quality bypass capacitors
(0.01F to 0.1F) in parallel with low ESR bypass capaci-
tors (1F to 10F tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (e.g., 1.5GΩ of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum IB– specification).
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs: for inverting configurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below).
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
APPLICATIONS INFORMATION
VS = ±15V
1469 G37
VS = ±15V
1469 G38
VS = ±15V
1469 G39
VS = ±15V
1469 G40
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