參數(shù)資料
型號(hào): LT1431MJ8#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 基準(zhǔn)電壓源/電流源
英文描述: 1-OUTPUT TWO TERM VOLTAGE REFERENCE, 2.5 V, CDIP8
封裝: 0.300 INCH, HERMETIC SEALED, LEAD FREE, CERAMIC, DIP-8
文件頁(yè)數(shù): 11/14頁(yè)
文件大?。?/td> 223K
代理商: LT1431MJ8#TRPBF
LT1431
6
1431fe
block DiagraM
pin FuncTions
COLL (Pin 1): Open collector of the output transistor. The
maximum pin voltage is 36V. The saturation voltage at
100mA is approximately 1V.
COMP (Pin 2): Base of the driver for the output transis-
tor. This pin allows additional compensation for complex
feedback systems and shutdown of the regulator. It must
be left open if unused.
V+ (Pin 3): Bias voltage for the entire shunt regulator.
The maximum input voltage is 36V and the minimum to
operate is equal to VREF (2.5V). The quiescent current is
typically 0.6mA.
RTOP (Pin 4): Top of the on-chip 5k-5k resistive divider
that guarantees 1% accuracy of operation as a 5V shunt
regulator with no external trim. The pin is tied to COLL for
self-contained 5V operation. It may be left open if unused.
See note on parasitic diodes below.
GND-S (Pin 5): Ground reference for the on-chip resis-
tive divider and shunt regulator circuitry except for the
output transistor. This pin allows external current limit
of the output transistor with one resistor between GND-F
(force) and GND-S (sense).
GND-F (Pin 6): Emitter of the output transistor and sub-
strate connection for the die.
RMID (Pin 7): Middle of the on-chip resistive divider string
between RTOP and GND-S. The pin is tied to REF for self-
contained 5V operation. It may be left open if unused.
REF (Pin 8): Control pin of the shunt regulator with a
2.5V threshold. If V+ > 3V, input bias current cancellation
reduces IB to 0.2A typical.
COMP,RTOP,RMID,andREFhavestaticdischargeprotection
circuits that must not be activated on a continuous basis.
Therefore, the absolute maximum DC voltage on these
pins is 6V, well beyond the normal operating conditions.
AswithallbipolarICs,theLT1431containsparasiticdiodes
which must not be forward biased or else anomalous
behavior will result. Pin conditions to be avoided are RTOP
below RMID in voltage and any pin below GND-F in voltage
(except for GND-S).
The following pin definitions apply to the Z package.
CATHODE: Corresponds to COLL and V+ tied together.
ANODE: Corresponds to GND-S and GND-F tied together.
REF: Corresponds to REF.
LT1431 BD
COMP
V+
GND-FORCE
GND-SENSE
RTOP
REF
RMID
2.5V
+
gm =
4mA/V
5k
COLLECTOR
8
7
5
4
3
2
1
6
5k
相關(guān)PDF資料
PDF描述
LT1460BIN8-2.5#TRPBF 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 2.5 V, PDIP8
LT1460EIN8-5#TRPBF 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 5 V, PDIP8
LT1460DCN8-5#TRPBF 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 5 V, PDIP8
LT1460ACN8-10#TRPBF 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, PDIP8
LT1460DCN8-10#TRPBF 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, PDIP8
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