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參數(shù)資料
| 型號(hào)： | LT1399IS#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CURRNT FEEDBK AMP TRPL 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | 電流反饋 |
| 電路數(shù)： | 3 |
| 轉(zhuǎn)換速率： | 800 V/µs |
| -3db帶寬： | 300MHz |
| 電流 - 輸入偏壓： | 10µA |
| 電壓 - 輸入偏移： | 1500µV |
| 電流 - 電源： | 4.6mA |
| 電流 - 輸出 / 通道： | 80mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 12 V，±2 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 管件 |
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10
LT1398/LT1399/LT1399HV
sn13989 13989fas
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Power Supplies
The LT1398/LT1399 will operate from single or split
supplies from
±2V (4V total) to ±6V (12V total). The
LT1399HV will operate from single or split supplies from
±2V (4V total) to ±7.5V (15V total). It is not necessary to
use equal value split supplies, however the offset voltage
and inverting input bias current will change. The offset
voltage changes about 600
V per volt of supply mis-
match. The inverting bias current will typically change
about 2
A per volt of supply mismatch.
Slew Rate
Unlike a traditional voltage feedback op amp, the slew rate
of a current feedback amplifier is not independent of the
amplifier gain configuration. In a current feedback ampli-
fier, both the input stage and the output stage have slew rate
limitations. In the inverting mode, and for gains of 2 or more
in the noninverting mode, the signal amplitude between the
input pins is small and the overall slew rate is that of the
output stage. For gains less than 2 in the noninverting mode,
the overall slew rate is limited by the input stage.
The input slew rate of the LT1398/LT1399/LT1399HV is
approximately 600V/
s and is set by internal currents and
capacitances. The output slew rate is set by the value of the
feedback resistor and internal capacitance. At a gain of 2
with 324
feedback and gain resistors and ±5V supplies,
the output slew rate is typically 800V/
s. Larger feedback
resistors will reduce the slew rate as will lower supply
voltages.
Enable/ Disable
Each amplifier of the LT1398/LT1399/LT1399HV has a
unique high impedance, zero supply current mode which
is controlled by its own EN pin. These amplifiers are
designed to operate with CMOS logic; the amplifiers draw
zero current when these pins are high. To activate each
amplifier, its EN pin is normally pulled to a logic low.
However, supply current will vary as the voltage between
the V + supply and EN is varied. As seen in Figure 1, +IS
does vary with (V + – VEN), particularly when the voltage
difference is less than 3V. For normal operation, it is
important to keep the EN pin at least 3V below the V +
supply. If a V + of less than 3V is desired, and the amplifier
will remain enabled at all times, then the EN pin should be
tied to the V – supply. The enable pin current is approxi-
mately 30
A when activated. If using CMOS open-drain
logic, an external 1k pull-up resistor is recommended to
ensure that the LT1399 remains disabled in spite of any
CMOS drain-leakage currents.
Figure 1. + IS vs (V
+ – VEN)
V + – VEN (V)
0
+I
S
(mA)
0.5
1.5
2.0
2.5
5.0
3.5
2
4
5
1398/99 F01
1.0
4.0
4.5
3.0
1
3
6
7
TA = 25°C
V + = 5V
V – = – 5V
V – = 0V
Figure 2. Amplifier Enable Time, AV = 2
VS = ±5V
VIN = 1V
RF = 324
RG = 324
RL = 100
1398/99 F02
OUTPUT
EN
Figure 3. Amplifier Disable Time, AV = 2
VS = ±5V
VIN = 1V
RF = 324
RG = 324
RL = 100
1398/99 F03
OUTPUT
EN
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