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參數(shù)資料
| 型號： | LT1394IS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR 7NS LOW PWR 8SOIC |
| 標準包裝： | 2,500 |
| 系列： | UltraFast™ |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，補充型，TTL |
| 電壓 - 輸入偏移（最小值）： | 2.5mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 4.5µA @ ±5V |
| 電流 - 輸出（標準）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 8.5mA |
| CMRR, PSRR（標準）： | 100dB CMRR，100dB PSRR |
| 傳輸延遲（最大）： | 9ns |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
13
LT1394
Fast, High Impedance, Variable Threshold Trigger
A frequent requirement in instrumentation is a fast trigger
with a variable threshold. Often, a high impedance input is
also required. Figure 15 meets these requirements. Com-
parator C1 is the basic trigger, with threshold voltage set at
its negative input. Source follower Q1 provides high
impedance with about 2pF input capacitance and 50pA bias
current. Normally, Q1’s source bias point would be uncer-
tain and drifty, but stabilization techniques eliminate this
concern. A1 measures filtered versions of Q1’s gate and
source voltages. A1’s output biases Q2, forcing Q1’s
channel current to whatever value is required to equalize
A1’s inputs, and hence Q1’s gate and source voltages. A1’s
input filtering and roll-off are far slower than input frequen-
cies of interest; its action does not interfere with the
circuit’s main signal path. The 330pF capacitor prevents
fast edges coupled through Q2’s collector base junction
from influencing A1’s operation.
APPLICATIONS INFORMATION
WU
U
Q1 should contribute negligible timing error to minimize
overall delay. Figure 16’s photo verifies Q1’s wideband
operation. Trace B, Q1’s source, lags the input (Trace A) by
only 300ps. Input, FET buffer output and C1 output appear
as Traces A, B and C, respectively in Figure 17. As before,
the FET buffer is seen to contribute small timing error, and
C1’s output is about 8ns delayed from the input.
–
+
C1
LT1394
–
+
A1
LT1097
10M
5V
VTRIG
±3V
0.01
F
0.1
F
OUTPUT
1394 F15
10k
Q2
2N3904
INPUT
±3V
Q1
2N5486
1.5k
–5V
0.1
F
10M
100
330pF
Figure 15. Buffer Provides 2pF, 50pA Input Characteristics for
Fast Trigger. Amplifier-Stabilized Biasing Eliminates FET Offset
200ps/DIV
1394 F16
Figure 16. Trigger Buffer’s 300ps Delay Minimizes
Timing Error. 4GHz Sampling Oscilloscope’s Output Is
a Series of Dots
A = 1V/DIV
B = 1V/DIV
Figure 17. Input (Trace A), FET Source (Trace B)
and Output (Trace C) Waveforms for the Trigger.
Total Delay Is 8ns
10ns/DIV
1394 F17
A = 1V/DIV
B = 1V/DIV
C = 2V/DIV
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| LT1395CS5#TR | 功能描述:IC AMP CURR FEEDBK SNGL TSOT23-5 RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:160 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:10 V/µs 增益帶寬積:9MHz -3db帶寬:- 電流 - 輸入偏壓:1pA 電壓 - 輸入偏移:250µV 電流 - 電源:730µA 電流 - 輸出 / 通道:28mA 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V，±1.35 V ~ 2.75 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:管件 |
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