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參數(shù)資料
| 型號(hào)： | LT1250 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SOIC 0 to 70 |
| 中文描述： | 極低噪聲零漂移放大器橋 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 230K |
| 代理商： | LT1250 |
6
LTC1250
where A
V
= closed-loop gain. Note that C
F
is not dependent
on the value of R
F
. Circuits with higher gain (A
V
> 50) or
low loop impedance should not require C
F
for stability.
C
F
frequency, approaching the best bipolar op amps at 10Hz
and surpassing them below 1Hz (Figure 1). All this is
accomplished in an industry-standard pinout; the LTC1250
requires no external capacitors, no nulling or clock sig-
nals, and conforms to industry-standard 8-pin DIP and 8-
pin SOIC packages.
Input Capacitance and Compensation
The large input transistors create a parasitic 55pF capaci-
tance from each input to V
+
. This input capacitance will
react with the external feedback resistors to form a pole
which can affect amplifier stability. In low gain, high
impedance configurations, the pole can land below the
unity-gain frequency of the feedback network and degrade
phase margin, causing ringing, oscillation, and other
unpleasantness. This is true of any op amp, however, the
55pF capacitance at the LTC1250’s inputs can affect
stability with a feedback network impedance as low as
1.9k. This effect can be eliminated by adding a capacitor
across the feedback resistor, adding a zero which cancels
the input pole (Figure 2). The value of this capacitor should
be:
C
A
V
U
S
A
O
PPLICATI
U
U
fully cancel the 1/f noise spectrum and the low frequency
noise of the part will rise. If the loop is underdamped (large
R
F
, no C
F
) it will ring for more than 150
μ
s and the noise
and offset will suffer.
The solution is to add C
F
as above but beware! Too large
a value of C
F
will overdamp the loop, again preventing it
from reaching a final value by the 150
μ
s deadline. This
condition doesn’t affect the LTC1250’s offset or output
stability, but 1/f noise begins to rise. As a rule of thumb,
the R
F
C
F
feedback pole should be
≥
7kHz (1/150
μ
s, the
frequency at which the loop settles) for best 1/f perfor-
mance; values between 100pF and 500pF work well with
feedback resistors below 100k. This ensures adequate
gain at 7kHz for the LTC1250 to properly null. High value
feedback resistors (above 1M) may require experimenta-
tion to find the correct value because parasitics, both in
the LTC1250 and on the PC board, play an increasing role.
Low value resistors (below 5k) may not require a capaci-
tor at all.
Input Bias Current
The inputs of the LTC1250, like all zero-drift op amps,
draw only small switching spikes of AC bias current; DC
leakage current is negligible except at very high tempera-
tures. The large front-end transistors cause switching
spikes 3 to 4 times greater than standard zero-drift op
amps: the
±
50pA bias current spec is still many times
better than most bipolar parts. The spikes don’t match
from one input pin to the other, and are sometimes (but
not always) of opposite polarity. As a result, matching the
impedances at the inputs (Figure 3) will not cancel the bias
current, and may cause additional errors. Don’t do it.
–
+
R
IN
1250 F02
LTC1250
R
F
C
P
Figure 2. C
F
Cancels Phase Shift Due to Parasitic C
P
Larger values of C
F
, commonly used in band-limited DC
circuits, may actually increase low frequency noise. The
nulling circuitry in the LTC1250 closes a loop that includes
the external feedback network during part of its cycle. This
loop must settle to its final value within 150
μ
s or it will not
pF
F
≥
55
–
+
R
IN
1250 F03
LTC1250
R
F
Figure 3. Extra Resistor Will NotCancel Bias Current Errors
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