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參數(shù)資料
| 型號： | LT1161 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-of-8 Data Selectors/Multiplexers With 3-State Outputs 16-SOIC 0 to 70 |
| 中文描述： | 四保護的高邊MOSFET驅(qū)動器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 290K |
| 代理商： | LT1161 |
7
LT1161
spike can play havoc with the power supply and false trip
the current-sense comparator.
Turn-on
V/
t is controlled by the addition of the simple
network shown in Figure 6. This network takes advantage
of the fact that the MOSFET acts as a source follower
during turn-on. Thus the
V/
t on the source can be
controlled by controlling the
V/
t on the gate:
V
t
V
10
V
C
TH
1
=
5
×
+
where V
TH
is the MOSFET gate threshold voltage. Multiply-
ing C
LOAD
times this
V/
t yields the value of the current
spike. For example, if V
+
= 24V, V
TH
= 2V, and C1 = 0.1
μ
F,
V/
t = 2.2V/ms, resulting in a 2.2A turn-on spike into
1000
μ
F. The diode and second resistor in the network
ensure fast current limit turn-off.
When turning off a capacitive load, the source of the
MOSFET can “hang up” if the load resistance does not
discharge C
LOAD
as fast as the gate is being pulled down.
If this is the case, a diode may have to be added from
source to gate to prevent V
GS(MAX)
from being exceeded.
and C
D
delay the overcurrent trip for drain currents up to
approximately 10
×
I
SET
, above which the diode conducts
and provides immediate turn-off (see Figure 7). To ensure
proper operation of the timer, C
D
must be
≤
C
T
.
MOSFET DRAIN CURRENT (1 = SET CURRENT)
1
T
D
C
D
)
10
1
0.1
0.01
10
100
L1161 F07
Printed Circuit Board Shunts
The sheet resistance of 1oz. copper clad is approximately
5
×
10
–4
/square with a temperature coefficient of
+0.39%/
°
C. Since the LT1161 drain sense threshold has a
similar temperature coefficient (+0.33%/
°
C), this offers
the possibility of nearly zero TC current sensing using
“free” drain sense resistors made out of PC trace material.
A conservative approach is to use 0.02" of width for each
1A of current for 1oz. copper. Combining the LT1161 drain
sense threshold with the 1oz. copper sheet resistance
results in a simple expression for width and length:
Width (1oz. Cu) = 0.02"
×
I
SET
Length (1oz. Cu) = 2"
The width for 2oz. copper would be halved while the length
would remain the same.
Bends may be incorporated into the resistor to reduce
space; each bend is equivalent to approximately 0.6
×
width of straight length. Kelvin connections should be
employed by running separate traces from the ends of the
resistors back to the LT1161 V
+
and sense pins. See
Application Note 53 for further information on printed
circuit board shunts.
Adding Current Limit Delay
When capacitive loads are being switched or in very noisy
environments, it is desirable to add delay in the drain
current-sense path to prevent false tripping (inductive
loads normally do not need delay). This is accomplished
by the current limit delay network shown in Figure 6. R
D
LT1161
24V
V
+
V
+
DS
C
D
C1
1161 F06
R
D
(
≤
10k)
1RFZ24
+
C
LOAD
CURRENT LIMIT
DELAY NETWORK
V/
t CONTROL NETWORK
1N4148
1N4148
100k
100k
G
+
Figure 6.
V/
t Control and Current Limit Delay
Figure 7. Current Limit Delay Time
APPLICATIO
S I
FOR
ATIO
U
W
U
U
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| LT1161C | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Quad Protected High-Side MOSFET Driver |
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| LT1161CN#PBF | 功能描述:IC MOSFET DRIVER N-CH QUAD 20DIP RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 外部開關(guān) 系列:- 標準包裝:5 系列:- 配置:低端 輸入類型:非反相 延遲時間:600ns 電流 - 峰:12A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導啟動）:- 電源電壓:14.2 V ~ 15.8 V 工作溫度:-20°C ~ 60°C 安裝類型:通孔 封裝/外殼:21-SIP 模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名稱:835-1063 |
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