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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LT1122BCN8 |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/14闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OP-AMP JFET FAST-SETTLNG 8DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | J-FET |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 80 V/µs |
| 澧炵泭甯跺绌嶏細 | 14MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 10pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 120µV |
| 闆绘祦 - 闆绘簮锛� | 7.5mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | ±5 V ~ 18 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-PDIP |
| 鍖呰锛� | 绠′欢 |
LT1122
5
1122fb
For more information www.linear.com/LT1122
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1122 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed up chip
temperature can be 10掳C to 50掳C higher than the ambient temperature.
Note 3: Settling time is 100% tested for A- and C-grades using the settling
time test circuit shown. This test is not included in quality assurance
sample testing.
Note 4: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 4mV
(A, B grades), to 5.7mV (C, D grades).
Note 5: Minimum supply voltage is tested by measuring offset voltage to
7mV maximum at 卤5V supplies.
Note 6: The LT1122 is not tested and not quality-assurance-sampled
at 鈥�40掳C and at 85掳C. These specifications are guaranteed by design,
correlation and/or inference from 鈥�55掳C, 0掳C, 25掳C, 70掳C and/or 125掳C
tests.
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15V
1F TANT
0.1F
1F TANT
0.1F
TYPICAL SUPPLY
BYPASSING FOR
EACH AMP/BUFFER
鈥�10V
(REGULATED)
1
2
TTL
IN
4
5
74LS00
GROUND ALL
OTHER INPUTS
10V
(REGULATED)
6
3
SETTLING
TIME OUTPUT
(20 TIMES SUM
NODE OUTPUT)
1k
NO CONNECTION ON PINS
10, 11, 12, 14, AND 15
1N5712
15V
鈥�15V
1.5k
LT1223
鈥�
+
3
2
4
7
6
8
1
7
2
5
4
1N5712
SUMMING
NODE
OUTPUT
鈥�15V
15V
*THIS RESISTOR CAN BE ADJUSTED TO
NULL OUT ALL OFFSETS AT THE SETTLING
TIME OUTPUT. THE AUTOMATED TESTER
USES A SEPARATE AUTOZERO CIRCUIT.
鈥�15V
(MEASURE INPUT
PULSE HERE)
VIN
5.1k
1%
4
鈥�15V
3
2
7
6
LT1122
2k
1%
15V
2k
1%
DEVICE UNDER TEST
5pF
15V
7
1
5
2
8
51
+
鈥�
HA5002
79
5.1k*
1%
HA5002
4
LTC201A
LT1122TA02
鈥�15V
+
Settling Time Test Fixture
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| RMCF1206JT2K20 | RES 2.2K OHM 1/4W 5% 1206 SMD |
| 151204-7422-TB | CONN HEADER 2MM 4POS DL R/A 30AU |
| HVF2512T2502FE | RES 25K OHM 1W 1% 2512 |
| RMCF1206JT1M00 | RES 1M OHM 1/4W 5% 1206 SMD |
| 77311-101-13LF | BERGSTIK |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LT1122BCN8#PBF | 鍔熻兘鎻忚堪:IC OP-AMP JFET FAST-SETTLNG 8DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:0.11 V/µs 澧炵泭甯跺绌�:350kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:4nA 闆诲 - 杓稿叆鍋忕Щ:20µV 闆绘祦 - 闆绘簮:260µA 闆绘祦 - 杓稿嚭 / 閫氶亾:20mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.7 V ~ 36 V锛�±1.35 V ~ 18 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SO 鍖呰:甯跺嵎 (TR) |
| LT1122BM | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
| LT1122BMJ8 | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
| LT1122CC | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
| LT1122CCJ8 | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
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