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參數(shù)資料
| 型號(hào)： | LSP2133CAD |
| 廠商： | LITE-ON SEMICONDUCTOR CORP |
| 元件分類： | 可調(diào)正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器 |
| 英文描述： | 1.2 V-5 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO5 |
| 封裝： | SOT-23, 5 PIN |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大小： | 516K |
| 代理商： | LSP2133CAD |
Liteon Semiconductor Corporation
LSP2133
300mA High PSRR Low Dropout CMOS Linear Regulator
4/8
Rev1.2
APPLICATION INFORMATION
Capacitor Selection and Regulator Stability
Similar to any low dropout regulator, the external capacitors used with the LSP2133 must be carefully selected for
regulator stability and performance.
Using a capacitor, CIN, whose value is＞1uF at the LSP2133 input pin, the amount of the capacitance can be
increased without limit. Please note that the distance between CIN and the input pin of the LSP2133 should not
exceed 0.5 inch. Ceramic capacitors are suitable for the LSP2133. Capacitors with larger values and lower ESR
provide better PSRR and line-transient response.
The LSP2133 is designed specifically to work with low ESR ceramic output capacitors in order to save space and
improve performance. Using an output ceramic capacitor whose value is ＞2.2μF with ESR＞5m ensure stability.
ADJ Output Voltage Programming
The output voltage of the LSP2133 adjustable regulator is programmed by using an external resistor divider as
shown in figure 1. The output voltage is calculated using:
Resistor R1 and R2 should be chosen for approximately 7uA divider current. Low value resistors can be used but
offer no advantage and waste more power. Higher value should be avoided as leakage current at ADJ pin increase
the output voltage error. Cc is unnecessary when R1 or R2 ＜20K. The recommended design procedure is to
choose R2=169k to set the divider current at 7uA and then calculated R1 using:
Load Transient Considerations
The figure7 shows the LSP2133 load transient response. It shows two components the output response: a DC shift
from the output impedance due to the load current change and transient response. The DC shift is quite small due to
excellent load regulation of the LSP2133. The transient spike, resulting from a step change in the load current from
1mA to 300mA, is 20mV. The ESR of the output capacitor is critical to the transient spike. A larger capacitance along
with smaller ESR results in a smaller spike.
Shutdown Input Operation
The LSP2133 is shutdown by pulling the EN input low, and is turned on by tying the EN input to VIN or leaving the
EN input floating.
Internal P-Channel Pass Transistor
The LSP2133 features a 0.75 P-Channel MOSFET device as a pass transistor. The P-MOS pass transistor
enables the LSP2133 to consume only 65μA of ground current during low dropout, light load, or heavy load
operations. This feature increases the battery operation life time.
Dropout Voltage
A regulator’s minimum dropout voltage determines the lowest usable supply voltage. The LSP2133 has a typical
300mV dropout voltage. In battery powered systems, this will determine the useful end-of-life battery voltage.
Current Limit and Short Circuit Protection
The LSP2133 features a current limit, which monitors and controls the gate voltage of the pass transistor. The output
current can be limited to 400mA by regulating the gate voltage. The LSP2133 also has a built-in short circuit current
limit.
Thermal Considerations
Thermal protection limits power dissipation in the LSP2133. When the junction temperature exceeds 150 , the OTP
(Over Temperature Protection) starts the thermal shutdown and turns the pass transistor off. The pass transistor
resumes operation after the junction temperature drops below 120 .
For continuous operation, the junction temperature should be maintained below 125 . The power dissipation is
defined as :
PD=(VIN-VOUT)*IO+VIN*IGND
The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of
surrounding airflow and temperature difference between junction and ambient. The maximum power dissipation can
be calculated by the following formula:
PD(MAX)=(TJ(MAX)-TA)/θJA
Where TJ(MAX) is the maximum allowable junction temperature 125 . TA is the ambient temperature and θJA is the
thermal resistance from the junction to the ambient.
For example, θJA is 250 /W for the SOT23-5L package, based on the standard JEDEC 51-3 for a single layer
thermal test board. The maximum power dissipation at TA=25
can be calculated by the following formula:
PD(MAX)= (125 -25 )/250=0.4W
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