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參數資料
| 型號： | LS5660-9PD6B1 |
| 元件分類： | 電源模塊 |
| 英文描述： | 2-OUTPUT 100 W AC-DC PWR FACTOR CORR MODULE |
| 封裝： | METAL, CASE S02, MODULE |
| 文件頁數： | 18/27頁 |
| 文件大小： | 599K |
| 代理商： | LS5660-9PD6B1 |
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Cassette Style
100 Watt AC-DC Converters
S Series PFC
Edition 01/01.2001
25/27
V ACFAIL Signal (VME)
Available for units with
Uo1 = 5.1V
This option denes an undervoltage monitoring circuit for
the input or input and main output voltage equivalent to op-
tion D and generates the ACFAIL signal (V signal) which
conforms to the VME standard.
The low state level of the ACFAIL signal is specied at a
sink current of
IV
≤ 48 mA to U
V
≤ 0.6 V (open-collector out-
put of a NPN transistor). The pull-up resistor feeding the
open-collector output should be placed on the VME back
plane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time
th of at least 4 ms before the 5.1 V
output drops to 4.875 V when the output is fully loaded.
This hold-up time
t h is provided by the internal input capaci-
tance. See also g.:
Hold-up Time versus Output Power.
Table 20: Undervoltage monitor functions
V output
Monitoring
Minimum adjustment
(VME compatible)
Ui
Uo1
range of threshold level
Uti
Uto
V2
yes
no
355V DC 1
–
V3
yes
355V DC 1 0.95...0.985
Uo1 2
1 Option D monitors the boost regulator output voltage. The trig-
ger level is adjusted in the factory to 355 V DC.
2 Fixed value between 95% and 98.5% of Uo1.
Vo1+
Vo1–
V
UV
IV
Rp
Input
11009
V output (V2, V3):
Connector pin V is internally connected to the open collec-
tor of a NPN transistor. The emitter is connected to the
negative potential of output 1.
UV
≤ 0.6 V (logic low) corre-
sponds to a monitored voltage level (
Ui and/or Uo1)
<U
t.
The current
IV through the open collector should not ex-
ceed 50 mA. The NPN output is not protected against ex-
ternal overvoltages.
UV should not exceed 60 V.
Ui, Uo1 status
V output,
UV
Ui or Uo1 < Ut
low, L,
UV ≤ 0.6 V at IV = 50 mA
Ui and Uo1 > Ut + Uh
high, H,
IV ≤ 25 A at UV = 5.1 V
Fig. 39
Output conguration of options V2 and V3
Option V operates independently of the built-in input under-
voltage lock-out circuit. A logic "low" signal is generated at
pin 20 as soon as one of the monitored voltages drops be-
low the preselected threshold level
Ut. The return for this
signal is Vo1–. The V output recovers when the monitored
voltage(s) exceed(s)
Ut + Uh. The threshold level Uti is ad-
justed in the factory to 355 V DC. The threshold level
Uto
either is adjusted during manufacture to a determined cus-
tomer specied value.
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