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參數(shù)資料
| 型號： | LS4001-9PV3 |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 100 W AC-DC PWR FACTOR CORR MODULE |
| 封裝： | HEAT SINK, METAL, CASE S02, MODULE |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 599K |
| 代理商： | LS4001-9PV3 |
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Cassette Style
100 Watt AC-DC Converters
S Series PFC
Edition 01/01.2001
23/27
Table 19: D-output logic signals
Version of D
Ui < Ut resp. Uo < Ut
Ui > Ut + Uh resp. Uo > Ut
Conguration
D1, D2, D3, D4, D0
low
high
JFET
D5, D6, D7, D8, D9, DD
high
low
NPN
D Undervoltage Monitor
The input and/or output undervoltage monitoring circuit op-
erates independently of the built-in input undervoltage lock-
out circuit. A logic "low" (JFET output) or "high" signal (NPN
output) is generated at pin 20 as soon as one of the moni-
tored voltages drops below the preselected threshold level
Ut. The return for this signal is Vo1–. The D output recovers
when the monitored voltage(s) exceed(s)
Ut + Uh. The
Table 18: Undervoltage monitoring functions
Output type
Monitoring
Minimum adjustment range
Typical hysteresis
Uho [% of Ut]
JFET
NPN
U i
Uo1
of threshold level
U t
for
U t min...U t max
Uti
Uto
Uho
D1
D5
no
yes
-
3.5...40 V 1
2.5...0.6
D2
D6
yes
no
355V DC 4
--
D3
D7
yes
355V DC 4
(0.95...0.985
Uo1) 2
"0"
D4
D8
no
yes
-
(0.95...0.985
Uo1) 2
"0"
D0
D9
no
yes
-
3.5...40 V 3
2.5...0.6
yes
355V DC 4
3.5...40 V 3
2.5...0.6
DD
yes
355V DC 4
3.5...40 V 1
2.5...0.6
1 Threshold level adjustable by potentiometer
2 Fixed value. Tracking if Uo1 adjusted via R-input, option P or sense lines.
3 The threshold level permanently adjusted according to customer specication
±2% at 25°C. Any value within the specied range is
basically possible but causes a special type designation in addition to the standard option designations (D0/D9)!
4 Option D monitors the boost regulator output voltage. The trigger level is adjusted in the factory to 355 V DC.
threshold level
Uti is adjusted in the factory. The threshold
level
Uto is either adjusted by a potentiometer, accessible
through a hole in the front cover, or factory adjusted to a
xed value specied by the customer.
Option D exists in various versions D0...DD as shown in the
following table.
Vo1+
Vo1–
D
UD
ID
Rp
Input
11007
Vo1+
Vo1–
D
UD
ID
Rp
Input
11006
Fig. 36
Option D0...D4: JFET output, ID ≤ 2.5 mA
NPN output (D5...DD):
Connector pin D is internally connected via the collector-
emitter path of a NPN transistor to the negative potential of
output 1.
UD
< 0.4 V (logic low) corresponds to a monitored
voltage level (
Ui and/or Uo1)
> U
t + Uh. The current ID
through the open collector should not exceed 20 mA. The
NPN output is not protected against external overvoltages.
UD should not exceed 40 V.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
high, H,
ID ≤ 25 A at UD = 40 V
Ui and Uo1 > Ut + Uh
low, L,
UD ≤ 0.4 V at ID = 20 mA
JFET output (D0…D4):
Connector pin D is internally connected via the drain-
source path of a JFET (self-conducting type) to the nega-
tive potential of output 1.
UD
≤ 0.4 V (logic low) corresponds
to a monitored voltage level (
Ui and/or Uo1)
<U
t. The cur-
rent
ID through the JFET should not exceed 2.5 mA. The
JFET is protected by a 0.5 W Zener diode of 8.2 V against
external overvoltages.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
low, L,
UD ≤ 0.4 V at ID = 2.5 mA
Ui and Uo1 > Ut + Uh
high, H,
ID ≤ 25 A at UD = 5.25 V
Fig. 37
Option D5...DD: NPN output, Uo1
≤ 40 V, I
D
≤ 20 mA
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