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參數(shù)資料
| 型號： | LS1501-9EPD4TB2 |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 100 W AC-DC REG PWR SUPPLY MODULE |
| 封裝： | METAL, CASE S02, MODULE |
| 文件頁數(shù)： | 16/25頁 |
| 文件大小： | 591K |
| 代理商： | LS1501-9EPD4TB2 |
Cassette Style
100 Watt AC-DC (DC-DC) Converters
S Series
Edition 01/01.2001
23/25
V ACFAIL signal (VME)
Available for units with
Uo1 = 5.1 V.
This option defines an undervoltage monitoring circuit for
the input or input and main output voltage equivalent to op-
tion D and generates an ACFAIL signal (V signal) which
conforms to the VME standard.
The low state level of the ACFAIL signal is specified at a
sink current of
IV ≤ 48 mA to UV ≤ 0.6 V (open-collector out-
put of a NPN transistor). The pull-up resistor feeding the
open-collector output should be placed on the VME back
plane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time
th of at least 4 ms before the 5.1 V
output drops to 4.875 V when the output is fully loaded. This
hold-up time
th is provided by the internal input capacitance.
Consequently the working input voltage and the threshold
level
Uti should be adequately above the minimum input
voltage
Ui min of the converter so that enough energy is re-
maining in the input capacitance.
Formula for threshold level for desired value of
th:
2
Po (th + 0.3 ms) 100
Uti =
––––––––––––––––––––– +
Ui min2
Ci min η
where as:
Ci min = internal input capacitance [mF]
Po
= output power [W]
η
= efficiency [%]
th
= hold-up time [ms]
Ui min = minimum input voltage [V] 1
Uti
= threshold level [V]
1 Min. input voltage according to: Electrical Input Data. For output
voltages
Uo > Uo nom, the minimum input voltage increases pro-
portionally to
Uo/Uo nom.
Remarks:
Option V2 and V3 can be adjusted by potentiometer to a
threshold level between
Ui min and Ui max.
Table 20: Available internal input capacitance and factory
potentiometer setting of Ut i with resulting hold-up time
Types
LS
Unit
Ci min
0.21
mF
Uti
120
V DC
th
6.4
ms
Option V operates independently of the built-in input under-
voltage lock-out circuit. A logic "low" signal is generated at
pin 20 as soon as one of the monitored voltages drops be-
low the preselected threshold level
Ut. The return for this
signal is Vo1–. The V output recovers when the monitored
voltage(s) exceed(s)
Ut + Uh. The threshold level Ut is either
adjustable by potentiometer, accessible through a hole in
the front cover, or is adjusted during manufacture to a de-
termined customer specified value.
Versions V0, V2 and V3 are available as shown below.
Table 21: Undervoltage monitor functions
V output
Monitoring
Minimum adjustment range
Typical hysteresis
Uh [% of Ut]
(VME compatible)
Ui
Uo1
of threshold level
for
Ut min…Ut max
Uti
Uto
Uhi
Uho
V2
yes
no
Ui min...Ui max 1
–
3.4...0.4
–
V3
yes
Ui min...Ui max 1
0.95...0.985
Uo1 2
3.4...0.4
"0"
V0
yes
no
Ui min...Ui max 3 4
–
3.4...0.4
–
yes
Ui min...Ui max 3 4
0.95...0.985
Uo1 2
3.4...0.4
"0"
1 Threshold level adjustable by potentiometer.
2 Fixed value between 95% and 98.5% of Uo1 (tracking).
3 Adjusted at Io nom.
4 Fixed value, resistor-adjusted (
±2% at 25°C) acc. to customer's specifications; individual type number is determined by Power-One.
V output (V0, V2, V3):
Connector pin V is internally connected to the open collec-
tor of a NPN transistor. The emitter is connected to the
negative potential of output 1.
UV
≤ 0.6 V (logic low) corre-
sponds to a monitored voltage level (
Ui and/or Uo1)
<U
t.
The current
IV through the open collector should not exceed
50 mA. The NPN output is not protected against external
overvoltages.
UV should not exceed 60 V.
Ui, Uo1 status
V output,
UV
Ui or Uo1 < Ut
low, L,
UV ≤ 0.6 V at IV = 50 mA
Ui and Uo1 > Ut + Uh
high, H,
IV ≤ 25 A at UV = 5.1 V
Vo1+
Vo1–
V
UV
IV
Rp
Input
11009
Fig. 36
Output configuration of options V0, V2 and V3
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