參數(shù)資料
型號(hào)： LRS1805A
廠商： Sharp Corporation
英文描述： Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM
中文描述： 堆疊芯片64M號(hào)（x16）的閃存16M內(nèi)存（× 16）Smartcombo內(nèi)存
文件頁(yè)數(shù)： 29/57頁(yè)
文件大?。?/td> 1373K
代理商： LRS1805A
LRS1805A
27
13. AC Electrical Characteristic for Smartcombo RAM
13.1 AC Test Conditions
Note:
1. Including scope and socket capacitance.
13.2 Read Cycle
(1,2,3)
(T
A
= -25°C to +85°C, S-V
CC
= 2.7V to 3.1V)
Notes
Min.
Notes:
It is possible to control data width by S-LB and S-UB pins.
1. Reading data from lower byte
Data can be read when the address is set while holding S-CE
1
= Low, S-CE
2
= High, S-OE = Low, S-WE = High and
S-LB = Low.
2. Reading data from upper byte
Data can be read when the address is set while holding S-CE
1
= Low, S-CE
2
= High, S-OE = Low, S-WE = High and
S-UB = Low.
3. Reading data from both bytes
Data can be read when the address is set while holding S-CE
1
= Low, S-CE
2
= High, S-OE = Low, S-WE = High,
S-LB = Low and S-UB = Low.
Input pulse level
0.3 V to V
CC
- 0.3 V
3 ns
1/2 V
CC
Input rise and fall time
Input and Output timing Ref. level
Output load
1TTL +C
L
(50pF)
(1)
Symbol
t
RC
t
AA
t
ACE
t
OE
t
BE
t
ASC
t
AHC
t
C1H
t
CLZ
t
CHZ
t
BLZ
t
BHZ
t
OLZ
t
OHZ
t
OH
Parameter
Max.
Unit
Read Cycle Time
85
32,000
ns
Address Access Time
85
ns
Chip Enable Access Time
85
ns
Output Enable to Output Valid
40
ns
Byte Enable Access Time
40
ns
Address Setup to S-CE
1
Low
Address Hold to S-CE
1
High
S-CE
1
High Pulse Width
S-CE
1
Low to Output Active
S-CE
1
High to Output in High-Z
0
ns
0
ns
30
ns
0
ns
30
ns
S-UB or S-LB Low to Output Active
0
ns
S-UB or S-LB High to Output in High-Z
30
ns
S-OE Low to Output Active
0
ns
S-OE High to Output in High-Z
30
ns
Output Hold from Address Change
5
ns
sharp
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