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參數資料
| 型號： | LR38620 |
| 廠商： | Sharp Corporation |
| 英文描述： | Timing Generator IC for 4200 k-pixwl CCD |
| 中文描述： | 時序發(fā)生器芯片CCD的4200的K - pixwl |
| 文件頁數： | 6/9頁 |
| 文件大?。?/td> | 95K |
| 代理商： | LR38620 |
LR38620
6
Serial Data Control
SERIAL DATA INPUT TIMING
ED
2
is shifted by the rising edge of ED
1
, and is
latched by the pulse #1 which is generated after
122 to 162 ns delay from the rising edge of ED
0
.
(See
Fig. 2
.)
The latched serial data are divided into two types
by the data of D
00
, and are relatched by the pulse
#2 which is generated after 203 to 243 ns delay
from the rising edge of ED
0
. (See
Fig. 1
.)
INMD is effective at the start of #3 horizontal line,
and shutter control data are effective at the start of
#11 horizontal line in monitoring mode and #93
horizontal line in still mode, and other data are
effective at pulse #2.
ED
0
should be at low level during data inputs of
ED
1
and ED
2
or while ACLX is at low level.
ED
0
ED
1
ED
2
D
22
D
21
D
23
D
24
D
20
D
19
D
18
D
17
D
16
D
15
D
14
D
09
D
10
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
D
11
D
12
D
13
Pulse #2
Pulse #1
ED
0
24.54545 MHz
244 ns min.
122 ns
203 ns
Fig. 1 Data Latch Timing
ED
0
ED
1
ED
2
OFDC
VH
3AX
VD
Monitoring
data input
period
10 ms min.
Mode
Monitoring
Still
Odd Field
Even Field
VH
1AX
from still mode to monitoring mode
data input period
5 μs min.
VD
HD
ED
0
5 μs min.
from monitoring mode
to still mode
Fig. 2 Input Pulse Timing of ED
0
, ED
1
and ED
2
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