- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358940 > LR38603 (Sharp Corporation) Digital Signal Processor for Color CCD Cameras PDF資料下載
參數(shù)資料
| 型號： | LR38603 |
| 廠商： | Sharp Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor for Color CCD Cameras |
| 中文描述： | 數(shù)字信號處理器的彩色CCD相機 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 160K |
| 代理商： | LR38603 |
LR38603
14
92h
93h
KEI_KEISU
ENCIN_PH
[7 : 0] Gain of PGA which produces KEI pulse.
[3]
Latch encoder clock inverted.
[2]
1 : Enable DFF.
[1 : 0] Delay adjustment of addition of luminance and color modulation.
(Delay of color signal)
00 : 0 clock delay to 11 : 3 clocks delay (delayed from "00" to "11" every 1
clock .) 1 clock : Original clock
[6 : 4] Delay adjustment of addition of luminance and color modulation.
(Delay of luminance signal)
101 : –3 clocks delay to 011 : 3 clocks delay (delayed from "101" to "011"
every 1 clock .)
1 clock : Pixel CK (complement of 2)
[3 : 0] Timing adjustment of luminance processing.
1001 : –7 clocks delay to 0111 : 7 clocks delay (delayed from "1001" to
"0111" every 1 clock.) 1 clock : Pixel CK (complement of 2)
[7]
Output 1/8 of original clock from DCK
1
.
[6]
Test mode. Set 0 in normal operation.
(The LR38603 does not read EEPROM and registers are set by serial data.)
[5]
Make D/A converter standby.
[4]
Swap R and B of color killer.
[3]
Swap R and B of white balance.
[2]
Swap R and B of matrix input.
[1]
Swap U and V of digital output.
[0]
Swap YL line selection for each R and B.
[7 : 0] Factor for white detect correction
[7 : 0] Factor for white detect correction
[7 : 0] Factor for white detect correction
[7 : 0] Factor for white detect correction
[7 : 0] Factor for black detect correction
[7 : 0] Factor for black detect correction
[7 : 0] Factor for black detect correction
VARI_ENC
94h
ANA_VARI
VARI_Y
95h
BUNSYU8_SEL
TEST
STDBY
CHG_CKIL
CHG_WB
CHG_MTX
CHG_CCD4
HG_YL_SEL
REF_AW
REF_BW
REF_CW
REF_DW
REF_AB
REF_BB
REF_CB
96h
97h
98h
99h
9Ah
9Bh
9Ch
ADDRESS
91h
NAME
BIT
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
CONTENTS
KNEE
INV_DCK2
INV_DCK1
BUSY_SEL
EI_ON_SEL
HRI_SEL
VRI_SEL
IN_VRES
1 : Invert OBCP clock
1 : Invert DCK
2
1 : Invert DCK
1
1 : Reset auto control factor, when EEPSL is at H.
1 : Enable KEI pulse function.
1 : Invert HRES (minus attribute)
1 : Invert VRES (minus attribute)
Select vertical reset timing.
0 : Reset at CSYNC pulse timing.
1 : Reset at VD pulse timing.
相關PDF資料 |
PDF描述 |
|---|---|
| LR38616 | Timing Generator IC for 2 140 k-pixel CCDs |
| LR38620 | Timing Generator IC for 4200 k-pixwl CCD |
| LR38630 | Digital Signal Processor for CIF CMOS Image Cameras |
| LR38666Y | CMOS digital signal processor |
| LR4-260 | PolySwitch PTC Devices Overcurrent Protection Device |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LR38616 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Timing Generator IC for 2 140 k-pixel CCDs |
| LR38617 | 制造商:Sharp Microelectronics Corporation 功能描述:TIMING GENERATOR 48PQFP - Bulk |
| LR38620 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Timing Generator IC for 4200 k-pixwl CCD |
| LR38627 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Digital SIgnal Processing LSI for CCD |
| LR38630 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Digital Signal Processor for CIF CMOS Image Cameras |
發(fā)布緊急采購，3分鐘左右您將得到回復。