
LR38575
4
PIN NO.
SYMBOL
IO SYMBOL
POLARITY
PIN NAME
DESCRIPTION
20
V
DD3
–
Power supply
Supply of +3.3 V power.
An input pin for resetting all internal circuits at power-on.
Connect to V
DD
through the diode and GND through the
capacitor.
A pulse to sample-hold the signal for the CDS circuit.
The output polarity of RS is selected by serial data.
All clear input
ICU3
ACLX
21
–
A grounding pin.
An input pin to control internal vertical clock for long
shutter speed.
H level or open
: VD
L level
: VD is masked by the pulse which
is latched at the rising edge of VD.
It's necessary to be set SMD = high and number of the
fields data n ≥ 2 in serial data control at VCON operation.
An input pin for reference clock oscillation.
The frequency is 24.54545 MHz.
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
An output pin to generate HD and VD pulses.
The frequency is 12.272725 MHz.
Ground
–
GND
23
22
RS
O6MA3
S/H pulse output
24
VCON
ICU3
VD control input
–
–
A pulse to sample-hold the signal for the CCD.
The output phase and output polarity of FS are selected
by serial data.
CDS pulse output 2
O6MA3
FS
19
–
–
Clock input
OSCI3
CKI
25
26
CKO
OSCO3
Clock output
–
Clock output
O6MA3
CLK
27
18
FCDS
O6MA3
CDS pulse output 1
A pulse to clamp the feed-through level for the CCD.
The output phase and output polarity of FCDS are
selected by serial data.
A pulse to clamp the optical black signal.
This pulse is controlled by serial data BCPCNT;
BCPCNT = H; This pulse stays high during the
absence of effective pixels within the
vertical blanking or during the
sweepout signal.
BCPCNT = L; This pulse stays high during the
sweepout signal.
A pulse to clamp the dummy outputs of the CCD signal.
This pulse stays high during the sweepout period.
An output pin for AD converter. The output phase of
ADCK is selected by serial data in 90 steps.
A grounding pin.
Optical black clamp
pulse output
BCPX
14
O3
O3
15
CLPX
Clamp pulse output
AD clock output
ADCK
16
O6MA3
–
17
GND
Ground
–