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參數(shù)資料
| 型號： | LPC47M172-NR |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 20 MM, 2.7 MM HEIGHT, MQFP-128 |
| 文件頁數(shù)： | 87/228頁 |
| 文件大小： | 1269K |
| 代理商： | LPC47M172-NR |
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6.
SMSC DS – LPC47M192
Page 87
Rev. 03/30/05
DATASHEET
a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has
not already done so, the peripheral should latch the information byte now.
b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no
more wait states are required followed by the TAR to complete the write cycle.
Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
Chip may modify nWRITE and nPDATA in preparation for the next cycle.
7.
8.
EPP 1.9 Read
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states
into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can
complete under the following circumstances:
1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can
complete when nWAIT goes inactive high.
2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before
changing the state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT
is determined inactive.
Read Sequence of Operation
1.
The host initiates an I/O read cycle to the selected EPP register.
2.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
3.
The chip tri-states the PData bus and deasserts nWRITE.
4.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal
is valid.
5.
Peripheral drives PData bus valid.
6.
Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
7. a)
The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or
nADDRSTRB. This marks the beginning of the termination phase.
b) The chip drives the sync that indicates that no more wait states are required and drives valid data onto the
LAD[3:0] signals, followed by the TAR to complete the read cycle.
8.
Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated.
9.
Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also
available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-
directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction
is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required
to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to
the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in
Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to
zero. Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read.
EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle.
The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used
to extend the cycle time. The write cycle can complete when nWAIT is inactive high.
Write Sequence of Operation
1. The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
2. The host initiates an I/O write cycle to the selected EPP register.
3. The chip places address or data on PData bus.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the
WRITE signal is valid.
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| LPC47M182-NR | ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47M172-NW | 功能描述:輸入/輸出控制器接口集成電路 Enhanced Super I/O Contrllr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47M182 | 制造商:SMSC 制造商全稱:SMSC 功能描述:ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC |
| LPC47M182_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Advanced I/O Controller with Motherboard GLUE Logic |
| LPC47M182E-NW | 功能描述:輸入/輸出控制器接口集成電路 Advanced I/O Ctrl MotherBoard GLUE RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47M182-NR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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