
SMSC DS – LPC47M14X 
Page 111 
Rev. 03/19/2001 
6.14.2 
Each GPIO port has a 1-bit data register and an 8-bit configuration control register.  The data register for each GPIO 
port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6.  The bits in these registers reflect 
the value of the associated GPIO pin as follows.  Pin is an input: The bit is the value of the GPIO pin.  Pin is an 
output:  The value written to the bit goes to the GPIO pin.  Latched on read and write.  All of the GPIO registers are 
located in the PME block see “Run Time Register” section.  The GPIO ports with their alternate functions and 
configuration state register addresses are listed in Table 54. 
Description 
Table 54  –  General Purpose I/O Port Assignments 
PIN # 
QFP 
DEFAULT 
FUNCTION 
ALT. FUNC. 1 
ALT. 
FUNCTION
2 
ALT. 
FUNCTION 
3 
DATA 
REGISTER
1
DATA 
REGISTER 
BIT NO. 
0 
1 
2 
3 
4 
5 
6 
7 
0 
1 
2 
3 
4 
5 
6 
7 
0 
1 
2 
3 
4 
5 
6 
7 
0 
1 
2 
REGISTER 
OFFSET 
(HEX) 
4B 
32 
33 
34 
35 
36 
37 
38 
39 
41 
42 
43 
N/A 
45 
46 
47 
50 
51 
52 
54 
55 
61 
62 
63 
64 
1 
2 
17 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
Reserved 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
Infrared Rx 
Infrared Tx 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
Joystick 1 Button 1 
Joystick 1 Button 2 
Joystick 2 Button 1 
Joystick 2 Button 2 
Joystick 1 X-Axis 
Joystick 1 Y-Axis 
Joystick 2 X-Axis 
Joystick 2 Y-Axis 
P17 
P16 
P12 
System Option 
MIDI_IN 
MIDI_OUT 
SMI Output 
Fan Tachometer 2 
Fan Tachometer 1 
Fan Speed Control 2 
Fan Speed Control 1 
GPIO 
GPIO 
Keyboard Reset 
Gate A20 
Drive Density Select 0 
Drive Density Select 1 
Power Management 
Event 
Device Disable Reg. 
Control 
Ring Indicator 2 
Data Carrier Detect 2 
Receive Serial Data 2 
Transmit Serial Data 2 
Data Set Ready 2 
Request to Send 2 
Clear to Send 2 
Date Terminal Ready 
LED 
LED 
GP1 
EETI 
EETI 
EETI 
GP2 
4C 
GP3 
4D 
28 
GPIO 
EETI 
3 
N/A 
92 
94 
95 
96 
97 
98 
99 
100 
48 
49 
N/A 
Reserved 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
GPIO 
Reserved 
GP4 
7:4 
0 
1 
2 
3 
4 
5 
6 
7 
0 
1 
7:2 
4E 
GP5 
GP6 
4F 
97 
98 
99 
100 
50 
EETI 
EETI 
Note 1:
The GPIO Data and Configuration Registers are located in PME block at the offset shown  
from the PME_BLK address.