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參數(shù)資料
| 型號： | LPC3180 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface |
| 中文描述： | 16/32位ARM微控制器，硬件的浮點(diǎn)協(xié)處理器的USB On - The - Go的，和SDRAM存儲器接口 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | LPC3180 |
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LPC3180_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 2 June 2006
23 of 36
Philips Semiconductors
LPC3180
16/32-bit ARM microcontroller with external memory interface
Counter or Timer operation.
Two 32-bit capture registers.
Three 32-bit match registers that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
Pause control to stop counting when core is in debug state.
6.19 Millisecond timer
The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to
obtain a lower count rate.
The millisecond timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter
either continue to run, stop, or be reset.
6.19.1
Features
32-bit Timer/Counter, running from the 32 kHz RTC clock.
Counter or Timer operation.
Three 32-bit match registers that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
Pause control to stop counting when core is in debug state.
6.20 Watchdog timer
The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit
counter. A match register is compared to the Timer. When configured for watchdog
functionality, a match drives the match output low. The match output is gated with an
enable signal that gives the opportunity to generate two type of reset signal: one that only
resets chip internally, and another that goes through a programmable pulse generator
before it goes to the external pin RESOUT_N and to the internal chip reset.
6.20.1
Features
Programmable 32-bit timer.
Internally resets the device if not periodically reloaded.
Flag to indicate that a watchdog reset has occurred.
Programmable watchdog pulse output on RESOUT_N pin.
Can be used as a standard timer if watchdog is not used.
Pause control to stop counting when core is in debug state.
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