參數(shù)資料
型號: LPC2930FBD208
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 flashless microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, MROM, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝: 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT459-1, LQFP-208
文件頁數(shù): 18/98頁
文件大?。?/td> 643K
代理商: LPC2930FBD208
LPC2930_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 April 2010
18 of 98
NXP Semiconductors
LPC2930
ARM9 microcontroller with CAN, LIN, and USB
6.6.2
Base clock and branch clock relationship
Table 7
contains an overview of all the base blocks in the LPC2930 and their derived
branch clocks. A short description is given of the hardware parts that are clocked with the
individual branch clocks. In relevant cases more detailed information can be found in the
specific subsystem description. Some branch clocks have special protection since they
clock vital system parts of the device and should not be switched off. See
Section 6.14.5
for more details of how to control the individual branch clocks.
Fig 4.
LPC2930 overview of clock areas
TIMER0/1 MTMR
PWM0/1/2/3
ADC0/1/2
QEI
modulation and sampling
control subsystem
BASE_MSCSS_CLK
branch
clocks
branch
clocks
BASE_ADC_CLK
BA SE_ICLK0_CLK
BASE_ICLK1_CLK
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
LIN0/1
I2C0/1
networking subsystem
BASE_IVNSS_CLK
branch
clocks
RESET/CLOCK
GENERATION
POWER
MANAGEMENT
power control subsystem
BASE_PCR_CLK
branch
clock
GPIO0/1/2/3/4/5
TIMER 0/1/2/3
SPI0/1/2
UART0/1
WDT
BASE_SYS_CLK
CPU
AHB MULTILAYER MATRIX
VIC
GPDMA
USB REGISTERS
SRAM/SMC
general subsytem
peripheral subsystem
AHB TO APB BRIDGES
SYSTEM CONTROL
EVENT ROUTER
CFID
branch
clocks
branch
clock
branch
clock
branch
clock
BASE_SAFE_CLK
BASE_UART_CLK
BASE_SPI_CLK
BASE_TMR_CLK
002aae260
CGU0
CGU1
BASE_USB_CLK
BASE_USB_I2C_CLK
BASE_OUT_CLK
USB
CLOCK
OUT
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