參數(shù)資料
型號: LPC2458FET180
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-bit-32-bit micro; 512 kB flash, Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
封裝: LPC2458FET180<SOT570-3 (TFBGA180)|<<http://www.nxp.com/packages/SOT570-3.html<1<Always Pb-free,;
文件頁數(shù): 72/80頁
文件大?。?/td> 611K
代理商: LPC2458FET180
LPC2458
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 September 2011
72 of 80
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors C
x1
, C
x2
, and C
x3
in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of C
x1
and C
x2
should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
14.5 Standard I/O pin configuration
Figure 29
shows the possible pin modes for standard I/O pins with analog input function:
Digital output driver
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Analog input (for ADC input channels)
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Fig 29. Standard I/O pin configuration with analog input
PIN
V
DD
ESD
V
SS
ESD
V
DD
weak
pull-up
weak
pull-down
output enable
output
pull-up enable
pull-down enable
data input
analog input
select analog input
002aaf496
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
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