參數(shù)資料
型號: LPC2420FET208
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
中文描述: 16-BIT, 72 MHz, RISC MICROCONTROLLER, PBGA208
封裝: 15 X 15 MM, 0.70 MM HEIGHT, PLASTIC, SOT-950-1, TFBGA-208
文件頁數(shù): 2/86頁
文件大?。?/td> 496K
代理商: LPC2420FET208
LPC2420_60
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6.1 — 22 September 2011
2 of 86
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as single data rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I
2
S, and SD/MMC interface as well as for memory-to-memory transfers.
Serial Interfaces:
Ethernet MAC with MII/RMII interface and associated DMA controller (LPC2460
only). These functions reside on an independent AHB.
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels (LPC2460 only).
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
Other peripherals:
SD/MMC memory card interface.
160 General purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC.
Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
RTC with separate power domain. Clock source can be the RTC oscillator or the
APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, port 0/2
pin interrupt, Ethernet wake-up interrupt (LPC2460 only), CAN bus activity (LPC2460
only)).
Two independent power domains allow fine tuning of power consumption based on
needed features.
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LPC2458FET180 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
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