參數(shù)資料
型號(hào): LPC2294HBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontrollers; 256 kB ISP-IAP flash with CAN, 10-bit ADC and external memory interface
封裝: LPC2292FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2292FET144/01<SOT569-1 (TFBGA144)|<<http://www.nxp.com/packages/SOT56
文件頁(yè)數(shù): 10/54頁(yè)
文件大?。?/td> 428K
代理商: LPC2294HBD144
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
10 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P0[27]/AIN0/
CAP0[1]/
MAT0[1]
23
[6]
H3
[6]
I
AIN0 —
ADC, input 0. This analog input is always connected
to its pin.
CAP0[1] —
Capture input for Timer 0, channel 1.
MAT0[1] —
Match output for Timer 0, channel 1.
AIN1 —
ADC, input 1. This analog input is always connected
to its pin.
CAP0[2] —
Capture input for Timer 0, channel 2.
MAT0[2] —
Match output for Timer 0, channel 2.
AIN2 —
ADC, input 2. This analog input is always connected
to its pin.
CAP0[3] —
Capture input for Timer 0, Channel 3.
MAT0[3] —
Match output for Timer 0, channel 3.
AIN3 —
ADC, input 3. This analog input is always connected
to its pin.
EINT3 —
External interrupt 3 input.
CAP0[0] —
Capture input for Timer 0, channel 0.
Port 1:
Port 1 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 1 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 2 through 15 of port 1 are not available.
CS0 —
LOW-active Chip Select 0 signal.
(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)
OE —
LOW-active Output Enable signal.
TRACEPKT0 —
Trace Packet, bit 0. Standard I/O port with
internal pull-up.
TRACEPKT1 —
Trace Packet, bit 1. Standard I/O port with
internal pull-up.
TRACEPKT2 —
Trace Packet, bit 2. Standard I/O port with
internal pull-up.
TRACEPKT3 —
Trace Packet, bit 3. Standard I/O port with
internal pull-up.
TRACESYNC —
Trace Synchronization. Standard I/O port
with internal pull-up.
Note:
LOW on this pin while RESET is LOW, enables pins
P1[25:16] to operate as Trace port after reset.
PIPESTAT0 —
Pipeline Status, bit 0. Standard I/O port with
internal pull-up.
PIPESTAT1 —
Pipeline Status, bit 1. Standard I/O port with
internal pull-up.
PIPESTAT2 —
Pipeline Status, bit 2. Standard I/O port with
internal pull-up.
TRACECLK —
Trace Clock. Standard I/O port with internal
pull-up.
I
O
I
P0[28]/AIN1/
CAP0[2]/
MAT0[2]
25
[6]
J1
[6]
I
O
I
P0[29]/AIN2/
CAP0[3]/
MAT0[3]
32
[6]
L1
[6]
I
O
I
P0[30]/AIN3/
EINT3/CAP0[0]
33
[6]
L2
[6]
I
I
I/O
P1[0] to P1[31]
P1[0]/CS0
91
[7]
G11
[7]
O
P1[1]/OE
P1[16]/
TRACEPKT0
P1[17]/
TRACEPKT1
P1[18]/
TRACEPKT2
P1[19]/
TRACEPKT3
P1[20]/
TRACESYNC
90
[7]
34
[7]
G13
[7]
L3
[7]
O
O
24
[7]
H4
[7]
O
15
[7]
F2
[7]
O
7
[7]
D2
[7]
O
102
[7]
D12
[7]
O
P1[21]/
PIPESTAT0
P1[22]/
PIPESTAT1
P1[23]/
PIPESTAT2
P1[24]/
TRACECLK
95
[7]
F11
[7]
O
86
[7]
H11
[7]
O
82
[7]
J11
[7]
O
70
[7]
L11
[7]
O
Table 4.
Symbol
Pin description
…continued
Pin (LQFP)
Pin
(TFBGA)
[1]
Type
Description
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