參數(shù)資料
型號: LPC2210FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface
中文描述: 16/32位的ARM微控制器;閃存less,10位ADC和外部存儲器接口
封裝: LPC2210FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2220FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.
文件頁數(shù): 13/50頁
文件大?。?/td> 259K
代理商: LPC2210FBD144
LPC2210_2220_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
13 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
P3.19/A19
P3.20/A20
P3.21/A21
P3.22/A22
P3.23/A23/
XCLK
46
[5]
45
[5]
44
[5]
41
[5]
40
[5]
L5
[5]
K5
[5]
N4
[5]
K4
[5]
N3
[5]
O
O
O
O
O
O
O
A19 —
External memory address line 19.
A20 —
External memory address line 20.
A21 —
External memory address line 21.
A22 —
External memory address line 22.
A23 —
External memory address line 23.
XCLK —
Clock output.
CS3 —
LOW-active Chip Select 3 signal.
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
CS2 —
LOW-active Chip Select 2 signal.
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
CS1 —
LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
WE —
LOW-active Write enable signal.
BLS3 —
LOW-active Byte Lane Select signal (Bank 3).
AIN7 —
ADC, input 7. This analog input is always connected
to its pin.
BLS2 —
LOW-active Byte Lane Select signal (Bank 2).
AIN6 —
ADC, input 6. This analog input is always connected
to its pin.
BLS1 —
LOW-active Byte Lane Select signal (Bank 1).
BLS0 —
LOW-active Byte Lane Select signal (Bank 0).
Not connected. This pin MUST NOT be pulled LOW or the
device might not operate properly.
External reset input:
A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Ground:
0 V reference.
P3.24/CS3
36
[5]
M2
[5]
P3.25/CS2
35
[5]
M1
[5]
O
P3.26/CS1
30
[5]
K2
[5]
O
P3.27/WE
P3.28/BLS3/
AIN7
29
[5]
28
[2]
K1
[5]
J4
[2]
O
O
I
P3.29/BLS2/
AIN6
27
[4]
J3
[4]
O
I
P3.30/BLS1
P3.31/BLS0
n.c.
97
[4]
96
[4]
22
[5]
E13
[4]
F10
[4]
H2
[5]
O
O
RESET
135
[6]
C5
[6]
I
XTAL1
142
[7]
C3
[7]
I
XTAL2
V
SS
141
[7]
3, 9, 26, 38,
54, 67, 79,
93, 103, 107,
111, 128
B3
[7]
C2, E4, J2,
N2, N7, L10,
K12, F13,
D11, B13,
B11, D7
C4
O
I
V
SSA
139
I
Analog ground:
0 V reference. This should nominally be the
same voltage as V
SS
, but should be isolated to minimize noise
and error.
PLL analog ground:
0 V reference. This should nominally be
the same voltage as V
SS
, but should be isolated to minimize
noise and error.
1.8 V core power supply:
This is the power supply voltage
for internal circuitry.
V
SSA(PLL)
138
B4
I
V
DD(1V8)
37, 110
N1, A12
I
Table 4.
Symbol
Pin description
…continued
Pin (LQFP)
Pin (TFBGA) Type
Description
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